[{"data":1,"prerenderedAt":401},["ShallowReactive",2],{"blog-microvia-pcb-guide-en":3,"header-nav-en":66},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":35,"slug":40,"jsonld":41},"PCB Microvias: Stacked vs Staggered Design and Reliability","Compare stacked and staggered PCB microvias, understand their manufacturing trade-offs, and specify useful reliability evidence for your design.","2026-11-11","technology","/assets/img/blogs/2026/11/microvia-cross-sections.jpg",9,1669,"PT9M","\u003Cp>A microvia can give a dense PCB layout an interlayer connection where a full-depth drilled hole uses too much space. For a connection across several layer transitions, stacked microvias save lateral area, while staggered microvias use an intermediate-layer connection and more room. The useful choice is the one that meets the routing requirement \u003Cstrong>and\u003C/strong> can be built and verified for the assembly and service conditions of the product.\u003C/p>\n\u003Cp>This discussion focuses on rigid boards. For the wider BGA escape decision, see the \u003Ca href=\"/en/blog/hdi-pcb-design-guide\">HDI PCB design guide\u003C/a>. Flexible circuits also have bend-zone concerns; see \u003Ca href=\"/en/blog/fpc-laser-drilling-microvias\">FPC laser microvias\u003C/a>.\u003C/p>\n\u003Ch2 id=\"what-is-a-microvia\" data-anchor-en=\"what-is-a-microvia\">What is a microvia?\u003C/h2>\n\u003Cp>A microvia is a small interlayer connection, often formed by laser drilling through dielectric to a target land, followed by metallization and copper plating. The precise definition, geometry and measurement rules depend on the applicable document and project requirements. A layer span such as L1 to L2 describes the connection more clearly than a drill diameter alone.\u003C/p>\n\u003Cp>\u003Cstrong>Stacked microvias\u003C/strong> place successive structures over one another. An upper via terminates on a prepared lower structure, so the interfaces within the vertical path matter to its integrity. \u003Cstrong>Staggered microvias\u003C/strong> are offset and joined by copper on an intermediate layer. They avoid directly stacking the vias, but the intermediate lands and connection need space.\u003C/p>\n\u003Cp>A plated through-hole travels through the board instead. It may still be the better solution if its diameter, lands and clearances fit the layout. The \u003Ca href=\"/en/blog/what-is-a-via-pcb\">PCB via introduction\u003C/a> covers the broader via family.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Option\u003C/th>\n\u003Cth>Routing effect\u003C/th>\n\u003Cth>Question to resolve\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Plated through-hole\u003C/td>\n\u003Ctd>Occupies space through the board and can affect routing or planes beyond the layers used\u003C/td>\n\u003Ctd>Can the unused layers accommodate the hole and required clearances?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Single microvia\u003C/td>\n\u003Ctd>Makes the specified local transition without a full-depth hole\u003C/td>\n\u003Ctd>Does that layer span complete the required connection?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Staggered path\u003C/td>\n\u003Ctd>Uses intermediate-layer land and copper to join offset vias\u003C/td>\n\u003Ctd>Is enough space available without disrupting other routes or a reference plane?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Stacked path\u003C/td>\n\u003Ctd>Puts successive structures and their interfaces in approximately the same footprint\u003C/td>\n\u003Ctd>How will the lower structure be prepared and how will the interfaces be verified?\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The stackup, layer spans, electrical requirements and fabricator's qualified construction matter more than the label alone. Neither stacked nor staggered is a universal reliability guarantee.\u003C/p>\n\u003Ch2 id=\"stacked-vs-staggered-an-l1-to-l3-example\" data-anchor-en=\"stacked-vs-staggered-an-l1-to-l3-example\">Stacked vs staggered: an L1-to-L3 example\u003C/h2>\n\u003Cp>Suppose a signal must travel from L1 to L3 on a rigid board that also has layers below L3. The following is a hypothetical comparison, not a tested design or a recommendation for a particular BGA.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Candidate\u003C/th>\n\u003Cth>Layout to check\u003C/th>\n\u003Cth>Fabrication and verification question\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Through-hole\u003C/td>\n\u003Ctd>Examine clearances and any unused hole portion on layers below L3, as well as the signal's electrical requirements.\u003C/td>\n\u003Ctd>Can the supplier build the required holes and lands with the proposed stackup?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Staggered\u003C/td>\n\u003Ctd>Connect an L1-L2 microvia to an offset L2-L3 microvia using L2 copper. Check the added lands and connection against nearby routes and reference-plane continuity.\u003C/td>\n\u003Ctd>Does the supplier's proposed sequence support both transitions, and does the evidence represent the actual path?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Stacked\u003C/td>\n\u003Ctd>Align the L1-L2 and L2-L3 structures. This removes the offset L2 connection, potentially freeing area, but adds a direct via-to-via interface.\u003C/td>\n\u003Ctd>How will the lower via be filled and its surface prepared, and what evidence covers that interface?\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>If the intermediate layer cannot accommodate the offset path, compare a stacked construction against other routing or stackup changes. If both fit, request feasibility and a quotation for each \u003Cstrong>complete board\u003C/strong>. More occupied space can affect board size or layer requirements; fill, registration, lamination, inspection and test requirements can also affect the build. A quote is meaningful only when both options describe comparable quantities and acceptance requirements.\u003C/p>\n\u003Ch2 id=\"how-are-microvias-made-and-where-can-problems-arise\" data-anchor-en=\"how-are-microvias-made-and-where-can-problems-arise\">How are microvias made, and where can problems arise?\u003C/h2>\n\u003Cp>A typical build-up process forms an opening to a target land, cleans and prepares it, deposits a conductive layer and plates copper to form the connection. A stack may add fill and surface preparation before the next build-up layer and upper via are made. The actual sequence depends on the materials, layer spans and fabricator's process.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/img/blogs/2026/11/microvia-cross-sections.jpg\" alt=\"Microscope cross-sections comparing microvia filling samples from a published laboratory study\">\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Feature or concern\u003C/th>\n\u003Cth>Why it matters\u003C/th>\n\u003Cth>What to clarify\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Laser opening and target alignment\u003C/td>\n\u003Ctd>Misalignment can reduce the intended overlap with the target land.\u003C/td>\n\u003Ctd>Which dimensions, registration allowance and target geometry has the supplier reviewed?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Target surface and copper interface\u003C/td>\n\u003Ctd>A weak interface can be difficult to detect before later thermal stress.\u003C/td>\n\u003Ctd>How is the target prepared, and what representative inspection or test is planned?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Copper plating and fill\u003C/td>\n\u003Ctd>Incomplete plating or a fill defect can affect the interconnect or the next stacked interface.\u003C/td>\n\u003Ctd>Which structures require fill, what finished condition is specified, and how will it be checked?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Sequential build-up\u003C/td>\n\u003Ctd>Added layer transitions depend on the proposed lamination and interconnect sequence.\u003C/td>\n\u003Ctd>Does the reviewed construction match the drawing and the supplier's intended build sequence?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Via in a solderable land\u003C/td>\n\u003Ctd>The exposed surface interacts with assembly as well as fabrication.\u003C/td>\n\u003Ctd>Agree on fill, cap, finish and land acceptance with both fabricator and assembler.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Do not transfer a hole size, aspect ratio, stack-height limit or fill requirement from a generic chart into a drawing without confirming it for the actual material, layer spacing and supplier process.\u003C/p>\n\u003Ch2 id=\"what-should-a-reliability-test-tell-you\" data-anchor-en=\"what-should-a-reliability-test-tell-you\">What should a reliability test tell you?\u003C/h2>\n\u003Cp>An electrical pass at room temperature is useful, but it describes the tested connections at that moment. IPC's 2019 warning documented examples of microvia failures found after bare-board fabrication and conventional acceptance, including during assembly or service. The warning identifies a failure risk in the reported cases; it does not say every stacked via will fail.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Evidence\u003C/th>\n\u003Cth>Useful answer\u003C/th>\n\u003Cth>Limit\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Room-temperature continuity\u003C/td>\n\u003Ctd>Is the tested path electrically continuous at that condition?\u003C/td>\n\u003Ctd>It may miss an intermittent opening that appears only during thermal exposure.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Microsection\u003C/td>\n\u003Ctd>What does the sampled construction look like at the examined plane?\u003C/td>\n\u003Ctd>A section is destructive and local; it cannot show the condition of every via or predict service life by itself.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Resistance monitored during a representative reflow simulation\u003C/td>\n\u003Ctd>Does the monitored path show an electrical change during the agreed thermal exposure?\u003C/td>\n\u003Ctd>Interpretation depends on specimen construction, measurement and acceptance rules; a passing coupon does not qualify the whole product.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Product qualification\u003C/td>\n\u003Ctd>Does the finished product meet its defined requirements for use?\u003C/td>\n\u003Ctd>This is a separate activity from bare-board fabrication acceptance.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>IPC-TM-650 method 2.6.27B describes convection reflow assembly simulation and representative specimens. The project team and supplier should identify the applicable document revision, exposure, measurement and acceptance criteria for the order. Do not treat a cycle count or resistance threshold from a general article as an automatic requirement for every product.\u003C/p>\n\u003Ch2 id=\"make-the-coupon-representative-of-the-path\" data-anchor-en=\"make-the-coupon-representative-of-the-path\">Make the coupon representative of the path\u003C/h2>\n\u003Cp>A useful coupon is not simply one that contains \u003Cem>some\u003C/em> microvias. Before the test, compare its material system, layer spans, stack arrangement, via and target geometry, fill, and fabrication sequence with the feature that matters on the board. Record differences and agree whether they affect the conclusion. A coupon on the same panel can support traceability, but proximity alone does not prove that it represents every feature.\u003C/p>\n\u003Cp>If a monitored path changes during the agreed thermal test, retain the waveform and identify the affected specimen and process lot. Agree on containment and failure analysis with the supplier; a microsection through the relevant feature may help investigate the mechanism, but the chosen section and sample still limit what can be seen. Do not release the construction on a room-temperature retest alone unless the project disposition permits it. For wider coupon planning, see \u003Ca href=\"/en/blog/pcb-test-coupons\">PCB test coupons\u003C/a>.\u003C/p>\n\u003Ch2 id=\"what-should-the-fabrication-package-include\" data-anchor-en=\"what-should-the-fabrication-package-include\">What should the fabrication package include?\u003C/h2>\n\u003Cp>Send the supplier the actual connection and the questions that remain open:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Layer path:\u003C/strong> fabrication files and drawing, stackup, layer names, required via spans, and locations of stacked, staggered and via-in-pad structures.\u003C/li>\n\u003Cli>\u003Cstrong>Construction:\u003C/strong> material and thickness requirements, target lands, proposed fill and cap where applicable, and any surfaces needed for soldering.\u003C/li>\n\u003Cli>\u003Cstrong>Electrical and layout constraints:\u003C/strong> critical nets, impedance or transition requirements, nearby routes, and reference-plane constraints.\u003C/li>\n\u003Cli>\u003Cstrong>Thermal history:\u003C/strong> the expected assembly process and relevant product exposure, so the team can decide what the test must represent.\u003C/li>\n\u003Cli>\u003Cstrong>Evidence and acceptance:\u003C/strong> applicable documents and revisions, agreed inspection, representative coupon construction, test conditions, acceptance criteria and traceability requirements.\u003C/li>\n\u003Cli>\u003Cstrong>Alternatives:\u003C/strong> identify where a staggered route, stacked path or conventional hole is still possible, and ask the supplier to flag required layout or stackup changes.\u003C/li>\n\u003C/ol>\n\u003Cp>Ask for the proposed construction and any deviations before releasing fabrication data. Coordinate solderable-land requirements with the assembler, and keep finished-product qualification separate from the fabricator's agreed acceptance evidence.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Cp>When the layer paths and open questions are ready, \u003Ca href=\"/en/quote\">request a quote\u003C/a> or \u003Ca href=\"/en/contact\">contact APTPCB\u003C/a> with the design package.\u003C/p>\n\u003Ch2 id=\"frequently-asked-questions\" data-anchor-en=\"frequently-asked-questions\">Frequently asked questions\u003C/h2>\n\u003Ch3 id=\"are-stacked-microvias-always-less-reliable\" data-anchor-en=\"are-stacked-microvias-always-less-reliable\">Are stacked microvias always less reliable?\u003C/h3>\n\u003Cp>No. Stacking adds interfaces and process dependencies that need attention, but performance depends on the actual materials, geometry, process and exposure. Compare representative evidence for the construction being proposed.\u003C/p>\n\u003Ch3 id=\"does-every-microvia-need-copper-fill\" data-anchor-en=\"does-every-microvia-need-copper-fill\">Does every microvia need copper fill?\u003C/h3>\n\u003Cp>No single fill rule covers every via. The required construction depends on the path, whether another via lands on it, the surface requirements and the fabricator's process. Specify and agree the finished feature rather than assuming a default.\u003C/p>\n\u003Ch3 id=\"does-a-passing-continuity-test-prove-microvia-reliability\" data-anchor-en=\"does-a-passing-continuity-test-prove-microvia-reliability\">Does a passing continuity test prove microvia reliability?\u003C/h3>\n\u003Cp>It confirms continuity of the tested path at the test condition. It does not alone establish behavior during assembly heating or throughout product life.\u003C/p>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/hdi-pcb-design-guide\">HDI PCB design guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/fpc-laser-drilling-microvias\">FPC laser microvias\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/what-is-a-via-pcb\">PCB via introduction\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-test-coupons\">PCB test coupons\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">request a quote\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact APTPCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32],{"id":15,"text":16},"what-is-a-microvia","What is a microvia?",{"id":18,"text":19},"stacked-vs-staggered-an-l1-to-l3-example","Stacked vs staggered: an L1-to-L3 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