[{"data":1,"prerenderedAt":408},["ShallowReactive",2],{"blog-pcb-fiducial-marks-en":3,"header-nav-en":72},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":41,"slug":46,"jsonld":47},"PCB Fiducial Marks: Placement, Panel Alignment and Assembly Handoff","Plan PCB fiducial marks for board, panel and local alignment, then verify visibility, coordinates and assembly handoff.","2026-11-05","manufacturing","/assets/img/blogs/2026/11/pcb-fiducial-panel-concept.png",14,2754,"PT14M","\u003Cp>A PCB fiducial mark is a visible reference feature that assembly equipment can use to locate a board or panel. A camera identifies the mark on the manufactured surface and relates its position to the digital placement data. Depending on the equipment and program, the measured references can help the assembler account for board position and rotation before components are placed.\u003C/p>\n\u003Cp>The useful question is not simply how many marks to add. It is \u003Cstrong>which physical surface the machine will see, which coordinates describe those marks, and whether the marks remain visible during the actual assembly step\u003C/strong>. A mark on a removable panel rail, a mark on each individual board and a mark near a critical package serve different purposes. Agree the arrangement with the assembler before releasing the fabrication and assembly files.\u003C/p>\n\u003Cp>For the larger array decision, see \u003Ca href=\"/en/blog/panelization-for-assembly\">panelization for assembly\u003C/a>. For component coordinates and rotation, see \u003Ca href=\"/en/blog/centroid-file-basics\">centroid file basics\u003C/a>. This article focuses on the optical reference marks that connect the manufactured board to those files.\u003C/p>\n\u003Cimg src=\"/assets/img/blogs/2026/11/pcb-fiducial-panel-concept.png\" alt=\"Conceptual assembly panel showing separate panel, board and package-area fiducial references\">\n\n\u003Cp>This drawing is conceptual and not to scale. \u003Cstrong>1\u003C/strong> indicates panel-level marks on the rail, \u003Cstrong>2\u003C/strong> indicates board-level marks on individual units, and \u003Cstrong>3\u003C/strong> indicates local marks near a component footprint. It is an illustration of different reference scopes, not a required count, layout or production drawing.\u003C/p>\n\u003Cimg src=\"/assets/img/blogs/2026/11/fiducial-marker-pcb-wdwd-retouched.png\" alt=\"Two round fiducial marks in square solder-mask clearances on an assembled green PCB, identified by red arrows\">\n\n\u003Cp>Two circular fiducial marks beside IC footprints on an assembled PCB; the red arrows indicate approximate locations. Photo: wdwd, CC BY-SA 3.0. AI-edited to remove chip branding; nearby details may have been reconstructed. Do not use this image as evidence for precise fiducial dimensions, geometry, or acceptance. \u003Ca href=\"/assets/credits/fiducial-marker-pcb-wdwd-retouched-credit.txt\">Image credit and modification note\u003C/a>.\u003C/p>\n\u003Ch2 id=\"what-does-the-camera-actually-use-a-fiducial-for\" data-anchor-en=\"what-does-the-camera-actually-use-a-fiducial-for\">What does the camera actually use a fiducial for?\u003C/h2>\n\u003Cp>Placement data describes intended component locations in a coordinate system. On the production line, a board can arrive shifted or rotated relative to the machine's working area. The equipment looks for selected recognizable features and uses the result in its alignment process. Which corrections are calculated, how many marks are used, and whether individual units or local areas are measured depend on the equipment and the programmed process.\u003C/p>\n\u003Cp>A visible target is only one input to placement accuracy. Board support, flatness, component handling, machine setup and the quality of the input data also matter. Texas Instruments' \u003Cem>Design Guide 92 NLA Array QFN\u003C/em> identifies fiducials, datum location, board size, flatness and mounting equipment among the factors affecting placement accuracy for the package discussed. A well-recognized mark does not independently prove correct component rotation, solder paste registration or finished solder joints.\u003C/p>\n\u003Cp>Do not confuse a fiducial with a \u003Cstrong>tooling hole\u003C/strong>. A tooling hole provides a mechanical feature for locating, supporting or handling a board or panel when the process uses it. A fiducial is an optical reference. Nor is a printed polarity symbol necessarily a machine-recognized fiducial: a camera program must know what feature to find and where to look.\u003C/p>\n\u003Ch2 id=\"panel-board-and-local-marks-answer-different-questions\" data-anchor-en=\"panel-board-and-local-marks-answer-different-questions\">Panel, board and local marks answer different questions\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Reference level\u003C/th>\n\u003Cth>What it can help locate\u003C/th>\n\u003Cth>A question to resolve before release\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Panel\u003C/td>\n\u003Ctd>The overall array presented to the machine.\u003C/td>\n\u003Ctd>Are the selected marks on a rail or another area the camera can see while the panel is held?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Individual board\u003C/td>\n\u003Ctd>A specific unit within the array.\u003C/td>\n\u003Ctd>Will the assembler measure each unit, use a panel transformation, or use another approved strategy?\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Local\u003C/td>\n\u003Ctd>The area associated with a particular component or region.\u003C/td>\n\u003Ctd>Does the package, equipment and process need a local reference, and where can it be observed without interfering with the footprint?\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>An array can contain marks at more than one level, but the presence of rail marks does not establish that every board position was individually measured. Conversely, marks on every unit do not mean that the line will use them. The assembly program and equipment capability determine the actual measurement strategy.\u003C/p>\n\u003Cp>Local marks are especially worth discussing when a component has demanding placement needs or when a large or flexible array may not be represented well enough by the selected overall references. Analog Devices' application note for its standard wire-bonded QFN packages recommends fiducial marks near the package to facilitate placement. That recommendation is specific guidance, not proof that every QFN or every machine requires the same local pattern. Ask the assembler how it plans to locate the relevant package and what evidence it uses to validate placement.\u003C/p>\n\u003Ch2 id=\"what-makes-a-mark-easy-to-recognize\" data-anchor-en=\"what-makes-a-mark-easy-to-recognize\">What makes a mark easy to recognize?\u003C/h2>\n\u003Cp>A fiducial needs a clear, repeatable appearance in the camera's field of view. An exposed copper feature with an appropriate surface finish is a common implementation. Around it, the solder mask opening and nearby features must allow the vision system to distinguish the intended target. A mark partly covered by solder mask, hidden under a component or visually confused with another feature may be difficult to locate even when its nominal coordinates are correct.\u003C/p>\n\u003Cp>Discuss the complete target with the assembler and fabricator:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Shape and size:\u003C/strong> Which geometry can the intended vision system recognize, and what finished size range is acceptable?\u003C/li>\n\u003Cli>\u003Cstrong>Mask opening:\u003C/strong> How much exposed area and surrounding clearance are needed after fabrication tolerances and mask registration are considered?\u003C/li>\n\u003Cli>\u003Cstrong>Optical background:\u003C/strong> Could nearby exposed copper, vias, text or surface features be mistaken for part of the target?\u003C/li>\n\u003Cli>\u003Cstrong>Finish and condition:\u003C/strong> Is the chosen surface finish compatible with the camera setup, and will the feature remain clean and visible through the relevant process steps?\u003C/li>\n\u003Cli>\u003Cstrong>Physical access:\u003C/strong> Can the camera see the mark when rails, clamps, carriers or previously mounted components are in place?\u003C/li>\n\u003C/ul>\n\u003Cp>As an example of source-specific guidance, Texas Instruments' \u003Cem>PCB layout for the TPA005D1x and TPA032D0x Class-D APAs\u003C/em> application note describes fiducial diameters of \u003Cstrong>1 to 1.5 mm\u003C/strong> for the board-design context it discusses. This is not an APTPCB capability statement, a universal tolerance or a substitute for the assembler's machine requirements. The same note discusses surrounding clearance and mask visibility; use the actual assembly specification to settle the complete geometry.\u003C/p>\n\u003Cp>The copper mark, solder mask opening and clearance around nearby objects are related but different dimensions. If a drawing says only “1 mm fiducial,” it does not tell the fabricator whether that number refers to the copper diameter, the mask opening or a required keep-out. Label each dimension and explain whether a clearance is measured from an edge or from the center. Review the final manufacturing outputs, not just the footprint name in the CAD library.\u003C/p>\n\u003Ch3 id=\"an-example-of-mark-opening-and-edge-clearance\" data-anchor-en=\"an-example-of-mark-opening-and-edge-clearance\">An example of mark, opening and edge clearance\u003C/h3>\n\u003Cp>Suppose a drawing shows the center of a circular fiducial \u003Cstrong>4.0 mm\u003C/strong> from a straight board edge and a concentric solder-mask opening \u003Cstrong>2.4 mm\u003C/strong> in diameter. The nominal distance from the edge of that opening to the board edge is \u003Cstrong>4.0 − 2.4 / 2 = 2.8 mm\u003C/strong>. The copper mark itself can have a different diameter; neither dimension should be assumed from the other.\u003C/p>\n\u003Cp>If, solely for this example, the fixture occupies the first \u003Cstrong>2.0 mm\u003C/strong> from that edge, the opening would have \u003Cstrong>0.8 mm\u003C/strong> of nominal clearance to the edge of that occupied zone. This arithmetic is not a recommended clearance or an APTPCB equipment specification. It omits manufacturing and positioning tolerances, fixture shape, camera field of view and any need for surrounding visual clearance. Ask the assembler to evaluate the actual mark, opening and clamped panel together.\u003C/p>\n\u003Ch2 id=\"where-should-the-marks-go-on-a-panel\" data-anchor-en=\"where-should-the-marks-go-on-a-panel\">Where should the marks go on a panel?\u003C/h2>\n\u003Cp>Start with how the product will travel through assembly. A board assembled as part of an array may be supported by rails that disappear during depanelization. Panel references can be placed in the available rail area when agreed, but check camera visibility against clamps, conveyor support, tooling holes and any printing or inspection fixtures. A mark on a rail is no longer available after that rail is removed.\u003C/p>\n\u003Cp>If a later operation handles separated boards, determine whether that operation needs references that remain on each unit. If the array has multiple board positions or different orientations, ask how each position is identified and how the placement program obtains its coordinates. Global panel alignment and individual-unit alignment are separate decisions; neither should be inferred from the word “panelized.”\u003C/p>\n\u003Cp>Place marks where they can be found consistently and where their relationship to the intended work area is useful to the equipment. Adequate spacing and a distinctive arrangement can make alignment and orientation easier to assess. As a discussion starting point, a designer might show three widely separated, non-collinear marks on the relevant board or panel. TI’s application note explains that two fiducials can provide position and rotation information; a third may support additional checks or corrections when the equipment is programmed to use it. This example is not a mandatory count or a guarantee that local distortion will be corrected. Verify the actual number, placement and correction model with the line owner.\u003C/p>\n\u003Cp>For two-sided assembly, review each side independently. The machine sees the physical side presented during that pass; a mark on the opposite face is not automatically visible. Confirm the flip convention, panel orientation, datum and coordinates used for each side, and identify any obstruction from components already mounted on the first side. A bottom-side image or coordinate export can be mirrored by different tools or workflows, so the meaning of the data must be agreed rather than guessed.\u003C/p>\n\u003Ch2 id=\"keep-board-coordinates-and-the-physical-panel-connected\" data-anchor-en=\"keep-board-coordinates-and-the-physical-panel-connected\">Keep board coordinates and the physical panel connected\u003C/h2>\n\u003Cp>A placement file may describe one board at its own origin, while a panel drawing describes repeated units on a larger array. The assembler may generate the array from the single-board data, receive panelized data, or use another agreed method. In each case, the program needs a consistent relationship among the fabrication layers, the board outline, the fiducials and the component coordinates.\u003C/p>\n\u003Cp>Use the release checklist below to record the coordinate conventions and physical references together.\u003C/p>\n\u003Cp>A fiducial does not need to appear as an ordinary placed component in every export format. Do not assume it will be present in the centroid file merely because it is visible in CAD. KiCad's PCB Editor documentation, for example, notes that a footprint excluded from position files will not appear in that export; its global and local fiducial fabrication attributes affect Gerber X2 output. Other software and export settings differ. Check the actual files and ask which mark list or drawing the assembler expects.\u003C/p>\n\u003Cp>If the paste stencil has its own optical references, agree how those relate to the board or panel references and the printer's setup. A stencil reference is not automatically an instruction to print solder paste onto a board fiducial. Review the paste layer and stencil drawing with the assembler so that alignment features and solder-paste apertures are not confused. The \u003Ca href=\"/en/pcba/pcb-stencil\">PCB stencil service page\u003C/a> describes the broader stencil handoff.\u003C/p>\n\u003Ch3 id=\"a-simple-coordinate-transformation\" data-anchor-en=\"a-simple-coordinate-transformation\">A simple coordinate transformation\u003C/h3>\n\u003Cp>Suppose a fiducial on a single board has coordinates \u003Cstrong>(12, 8) mm\u003C/strong> relative to the agreed board origin. For a hypothetical panel position, the board is rotated \u003Cstrong>90° counterclockwise about that origin\u003C/strong>, then translated by \u003Cstrong>(60, 30) mm\u003C/strong>. The rotation changes \u003Ccode>(x, y)\u003C/code> to \u003Ccode>(-y, x)\u003C/code>, giving \u003Ccode>(-8, 12) mm\u003C/code>; adding the translation gives a panel coordinate of \u003Cstrong>(52, 42) mm\u003C/strong>.\u003C/p>\n\u003Cp>This example only illustrates the arithmetic. It does not specify a production panel, machine rotation convention or bottom-side mirror. Before programming a real assembly, agree which direction is positive, the rotation point, the physical side being viewed and whether the file is already panelized. Check at least one component and the selected marks against the approved panel drawing; an accidentally repeated transformation can move every position even when the individual-board file was correct.\u003C/p>\n\u003Ch2 id=\"release-checklist-for-a-two-sided-array\" data-anchor-en=\"release-checklist-for-a-two-sided-array\">Release checklist for a two-sided array\u003C/h2>\n\u003Cp>Consider a small two-sided board repeated in an array: a fine-pitch device is on the top, and bottom-side components sit close to one edge. The board-level placement file omits fiducials, while the panel drawing shows rail marks and leaves the bottom-side view convention unspecified. These gaps do not prove that assembly will fail, but they leave setup decisions unresolved.\u003C/p>\n\u003Cp>Close the gaps with one matching release package:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Matching files:\u003C/strong> Include the fabrication outputs, board outline, assembly drawing, placement data, BOM and supplied panel drawing for the same board and panel revisions. Placement data should identify component reference designators, positions, rotations and packages.\u003C/li>\n\u003Cli>\u003Cstrong>Coordinate conventions:\u003C/strong> Record the origin, units, positive rotation direction, array positions and unit rotations. State the physical side being viewed, the bottom-side flip or mirror convention and whether placement data is already panelized.\u003C/li>\n\u003Cli>\u003Cstrong>Visible references:\u003C/strong> Identify the selected marks and their coordinates for each pass. Check that rails, clamps and previously mounted components leave those marks visible; identify references that must remain after depanelization.\u003C/li>\n\u003Cli>\u003Cstrong>Critical areas:\u003C/strong> Identify the fine-pitch device and other areas needing placement review. Resolve whether the selected process needs local marks and where they fit without encroaching on the footprint or inspection area.\u003C/li>\n\u003Cli>\u003Cstrong>Cross-check:\u003C/strong> Reconcile at least one known component and the selected fiducials against the board outline, panel drawing and placement data on both sides.\u003C/li>\n\u003Cli>\u003Cstrong>Ownership:\u003C/strong> Identify who creates the production panel, who approves the final placement program and who approves any panel or coordinate change. Release the matching files after resolving differences.\u003C/li>\n\u003C/ol>\n\u003Cp>The board arrangement is hypothetical. The checklist connects physical camera access to the exact data used for programming, including rail marks added by the assembler.\u003C/p>\n\u003Ch2 id=\"troubleshooting-alignment-questions\" data-anchor-en=\"troubleshooting-alignment-questions\">Troubleshooting alignment questions\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Observation during setup\u003C/th>\n\u003Cth>Questions to investigate\u003C/th>\n\u003Cth>Avoid assuming\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>The camera cannot find a target.\u003C/td>\n\u003Ctd>Is the correct side presented? Is the mark covered, obscured by a clamp, outside the search area or different from the programmed appearance?\u003C/td>\n\u003Ctd>That the component coordinates are the only problem.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Every placement appears shifted in the same direction.\u003C/td>\n\u003Ctd>Do the board origin, fiducial coordinates, units and panel transformation refer to the same revision and datum?\u003C/td>\n\u003Ctd>That moving individual component entries will correct the underlying frame mismatch.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>One unit in an array appears rotated.\u003C/td>\n\u003Ctd>Is that unit's panel rotation or orientation represented correctly in the setup data?\u003C/td>\n\u003Ctd>That a panel-level reference proves every unit's orientation.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>A critical package is misaligned while nearby parts appear acceptable.\u003C/td>\n\u003Ctd>Check the footprint, component rotation, local measurement strategy, board support and paste print for that area.\u003C/td>\n\u003Ctd>That adding a local fiducial alone will resolve the issue.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>One side works but the other does not.\u003C/td>\n\u003Ctd>Verify the physical flip, bottom-side view convention, data transformation and visible marks for the second pass.\u003C/td>\n\u003Ctd>That the bottom file uses the same viewing convention as the top file.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>These are diagnostic starting points. Preserve the files, programmed setup and observations so the responsible engineering team can isolate the actual cause. Inspection of the finished assembly remains separate from alignment of the incoming board.\u003C/p>\n\u003Cp>For a project-specific review, request a \u003Ca href=\"/en/quote\">quote\u003C/a> or \u003Ca href=\"/en/contact\">contact the team\u003C/a> with the release package above and the placement concerns to resolve. The assembler can assess its process and propose changes; the product team approves design changes and defines product-level acceptance.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"common-questions\" data-anchor-en=\"common-questions\">Common questions\u003C/h2>\n\u003Ch3 id=\"are-fiducials-required-for-every-pcb\" data-anchor-en=\"are-fiducials-required-for-every-pcb\">Are fiducials required for every PCB?\u003C/h3>\n\u003Cp>The need depends on how the board is assembled, the equipment and the agreed process. A hand-assembled prototype and a board processed by an automated line do not necessarily use the same alignment method. Confirm the intended process before leaving marks out or adding a standard pattern without review.\u003C/p>\n\u003Ch3 id=\"can-the-assembler-add-fiducials-after-the-layout-is-finished\" data-anchor-en=\"can-the-assembler-add-fiducials-after-the-layout-is-finished\">Can the assembler add fiducials after the layout is finished?\u003C/h3>\n\u003Cp>Rail-level features may be possible when the assembler controls panelization and sufficient space is available. A mark inside the finished board outline or near a component can require a design change. In either case, agree the physical feature, revision and data update; do not assume a supplier can alter the board or program without approval.\u003C/p>\n\u003Ch2 id=\"references\" data-anchor-en=\"references\">References\u003C/h2>\n\u003Cul>\n\u003Cli>Texas Instruments, \u003Cem>Design Guide 92 NLA Array QFN\u003C/em>, SLMA006, December 2012: factors affecting placement accuracy in the specified package context.\u003C/li>\n\u003Cli>Texas Instruments, \u003Cem>PCB layout for the TPA005D1x and TPA032D0x Class-D APAs\u003C/em>, SLYT012B: example fiducial geometry and visibility guidance in a particular board-design context.\u003C/li>\n\u003Cli>Analog Devices, \u003Cem>SMT Assembly and PCB Design Guidelines for Maxim's Standard Wire-Bonded QFN Packages\u003C/em>: package-specific placement and fiducial guidance.\u003C/li>\n\u003Cli>KiCad PCB Editor documentation: footprint attributes, mask and paste layers, and position-file export behavior; consult the documentation for the software version in use.\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/panelization-for-assembly\">panelization for assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/centroid-file-basics\">centroid file basics\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/pcb-stencil\">PCB stencil service page\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">quote\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact the team\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32,35,38],{"id":15,"text":16},"what-does-the-camera-actually-use-a-fiducial-for","What does the camera actually use a fiducial for?",{"id":18,"text":19},"panel-board-and-local-marks-answer-different-questions","Panel, board and local marks answer different questions",{"id":21,"text":22},"what-makes-a-mark-easy-to-recognize","What makes a mark easy to recognize?",{"id":24,"text":25},"where-should-the-marks-go-on-a-panel","Where should the marks go on a panel?",{"id":27,"text":28},"keep-board-coordinates-and-the-physical-panel-connected","Keep board coordinates and the physical panel connected",{"id":30,"text":31},"release-checklist-for-a-two-sided-array","Release checklist for a two-sided array",{"id":33,"text":34},"troubleshooting-alignment-questions","Troubleshooting alignment questions",{"id":36,"text":37},"common-questions","Common questions",{"id":39,"text":40},"references","References",[42,43,44,45],"PCB fiducial marks","SMT assembly","PCB panelization","pick and place","pcb-fiducial-marks",{"blog":48,"breadcrumb":57,"faq":71},{"@context":49,"@type":50,"headline":4,"description":5,"image":8,"url":51,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":52,"articleSection":7,"author":53,"publisher":56},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/pcb-fiducial-marks","PCB fiducial marks, SMT assembly, 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