[{"data":1,"prerenderedAt":401},["ShallowReactive",2],{"blog-pcb-layers-explained-en":3,"header-nav-en":65},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":35,"slug":39,"jsonld":40},"PCB Layers Explained: What Does a Four-Layer Board Really Have?","A four-layer PCB normally has four copper layers, while dielectric, solder mask, legend and design outputs have different functions.","2026-11-05","manufacturing","/assets/img/blogs/2026/11/pcb-layer-count-concept.svg",10,1962,"PT10M","\u003Cp>A four-layer PCB usually has \u003Cstrong>four layers of copper\u003C/strong>, not four total layers of material. Insulating material separates the copper, and the finished board may also have solder mask, printed markings and surface finish. Those physical materials matter, but they are not counted as additional copper layers.\u003C/p>\n\u003Cp>A PCB design file can contain even more “layers”: copper artwork, solder mask openings, paste apertures, board outlines and other instructions. Some describe materials that remain on the board; others tell a fabrication or assembly partner how to process it.\u003C/p>\n\u003Cp>For a basic introduction to the board itself, see \u003Ca href=\"/en/blog/what-is-a-pcb\">what is a PCB\u003C/a>. When ordering a multilayer board, the distinction matters because a correct layer count alone does not tell a fabricator which file belongs at each position, what each copper layer does or how the layers connect.\u003C/p>\n\u003Ch2 id=\"copper-count-versus-physical-construction\" data-anchor-en=\"copper-count-versus-physical-construction\">Copper count versus physical construction\u003C/h2>\n\u003Cp>Copper layers carry the board’s electrical features: traces, component pads, planes and other copper areas. A layer can contain signal routing, a ground plane, power distribution, or a combination. The count refers to distinct copper levels in the board, not to the number of nets or individual copper shapes.\u003C/p>\n\u003Cp>The insulation between copper layers is \u003Cstrong>dielectric material\u003C/strong>. In a rigid PCB, construction may include:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Core:\u003C/strong> cured insulating material, commonly supplied with copper foil bonded to one or both sides.\u003C/li>\n\u003Cli>\u003Cstrong>Prepreg:\u003C/strong> partially cured resin-reinforced material that can bond layers together during multilayer lamination.\u003C/li>\n\u003Cli>\u003Cstrong>Copper foil and plated copper:\u003C/strong> conductive material patterned to form the circuitry.\u003C/li>\n\u003Cli>\u003Cstrong>Solder mask and legend:\u003C/strong> coatings applied to the board surface, where specified.\u003C/li>\n\u003C/ul>\n\u003Cp>A normal two-copper-layer rigid board can begin with a copper-clad core: copper on each side of the insulating core. It does \u003Cstrong>not\u003C/strong> inherently need a separate prepreg layer between each foil and the core. Multilayer constructions can use prepreg to bond cores and other layers together. The actual material arrangement depends on the agreed stackup and manufacturing process.\u003C/p>\n\u003Cp>Likewise, a four-copper-layer board has more than four physical material regions. Calling it “four-layer” is useful shorthand for copper count, but it is not a complete construction specification.\u003C/p>\n\u003Cimg src=\"/assets/img/blogs/2026/11/pcb-layer-count-concept.svg\" alt=\"Concept illustration distinguishing PCB copper layers from other board and design layers\">\n\n\u003Cp>\u003Cem>Conceptual illustration, not to scale or a specification for an actual board. Copper count, insulating material and design-output layers describe different things.\u003C/em>\u003C/p>\n\u003Ch2 id=\"a-hypothetical-four-copper-layer-example\" data-anchor-en=\"a-hypothetical-four-copper-layer-example\">A hypothetical four-copper-layer example\u003C/h2>\n\u003Cp>Assume a rigid board has four copper layers, numbered from top to bottom:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Copper ID\u003C/th>\n\u003Cth>Hypothetical function\u003C/th>\n\u003Cth>What still needs confirmation\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>L1\u003C/strong>\u003C/td>\n\u003Ctd>Top-side signals and component pads\u003C/td>\n\u003Ctd>Connections, copper features and reference requirements for the actual design\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L2\u003C/strong>\u003C/td>\n\u003Ctd>Ground plane\u003C/td>\n\u003Ctd>Plane continuity, clearances and the nets that connect to it\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L3\u003C/strong>\u003C/td>\n\u003Ctd>Power distribution, signal routing, or both\u003C/td>\n\u003Ctd>Actual net assignments and whether the copper provides a suitable reference where needed\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L4\u003C/strong>\u003C/td>\n\u003Ctd>Bottom-side signals and component pads\u003C/td>\n\u003Ctd>Connections, routing and reference requirements for the actual design\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>This is an invented reference example, \u003Cstrong>not a universal stackup recipe\u003C/strong>. Another four-layer board may assign these functions differently. The names in the design, their physical order and the intended connections must be confirmed for the particular board.\u003C/p>\n\u003Cp>A four-layer arrangement can offer more routing space and opportunities to place reference copper near signal layers than a two-layer arrangement. It does not, by itself, prove acceptable electromagnetic interference, signal integrity or impedance. Those outcomes depend on factors including geometry, dielectric properties, return paths, discontinuities and the finished construction. A nearby plane is useful only when it supports the intended return path.\u003C/p>\n\u003Cp>For controlled-impedance work, provide the applicable traces, target values and tolerances along with an agreed stackup; do not infer a guarantee from “four-layer.” The \u003Ca href=\"/en/blog/pcb-stackup-design\">PCB stackup design\u003C/a> article addresses the construction choices in more detail.\u003C/p>\n\u003Ch3 id=\"how-vias-relate-to-the-layers\" data-anchor-en=\"how-vias-relate-to-the-layers\">How vias relate to the layers\u003C/h3>\n\u003Cp>A plated through-hole via can pass through the board, but passing through a copper layer is not the same as connecting electrically to it. At each layer, the design determines whether the via connects to a pad or copper area, or is isolated by clearance.\u003C/p>\n\u003Cp>In the hypothetical example, a via might join a signal on L1 to a signal on L4 while remaining clear of L2 and L3. A different via might connect ground copper where the design calls for it. Review the actual net and layer geometry rather than assuming that every via joins all four layers.\u003C/p>\n\u003Cp>Blind or buried vias have different start and end layers. If a design uses them, communicate those endpoints and requirements explicitly; four copper layers do not automatically imply that such vias are present or agreed.\u003C/p>\n\u003Ch2 id=\"mask-legend-and-paste-different-jobs\" data-anchor-en=\"mask-legend-and-paste-different-jobs\">Mask, legend and paste: different jobs\u003C/h2>\n\u003Cp>\u003Cstrong>Solder mask\u003C/strong> is a real coating, usually applied to the outer board surfaces. Its openings expose selected copper features, such as pads, for subsequent processing and assembly. Exposed copper may receive a specified surface finish; an opening should not be interpreted as a requirement to leave bare copper.\u003C/p>\n\u003Cp>Mask is not a substitute for a copper drawing. A mask opening identifies where coating should be absent; the copper artwork defines the conductive feature. An unintended opening can expose copper that was meant to remain covered, while a missing opening can cover a pad intended for soldering. See \u003Ca href=\"/en/blog/what-is-solder-mask\">what is solder mask\u003C/a> for more context.\u003C/p>\n\u003Cp>\u003Cstrong>Legend\u003C/strong>, often called silkscreen, is also a physical marking when applied. It may show reference designators, polarity indicators or other identification. It is not an electrical copper layer. If a marking conflicts with a pad or opening, resolve the intended treatment before release rather than relying on an assumption about what will be removed.\u003C/p>\n\u003Cp>A \u003Cstrong>paste layer\u003C/strong> generally describes aperture information for a solder-paste stencil. It is primarily an assembly output, not a permanent bare-board layer. During assembly, paste is deposited through stencil apertures and reflowed; the paste artwork itself is not a coating laminated into the PCB. A board or side with no applicable surface-mount paste requirements may not need a paste file, but that should be made clear to the assembly recipient.\u003C/p>\n\u003Cp>The distinction is also reflected in KiCad’s \u003Cem>Pcbnew Layers\u003C/em> documentation, which separates copper, mask, paste, legend and other design-layer purposes.\u003C/p>\n\u003Ch2 id=\"map-each-file-to-its-recipient\" data-anchor-en=\"map-each-file-to-its-recipient\">Map each file to its recipient\u003C/h2>\n\u003Cp>The following is an \u003Cstrong>illustrative transfer map\u003C/strong> for the hypothetical four-layer board above. File names are examples of descriptions, not required naming conventions. Confirm the actual names and formats with each recipient.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Output or information\u003C/th>\n\u003Cth>Purpose in this example\u003C/th>\n\u003Cth>Recipient and review condition\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>L1 top copper\u003C/strong>\u003C/td>\n\u003Ctd>Top pads and signal copper\u003C/td>\n\u003Ctd>Board fabricator; confirm it is the first copper layer and matches the top-side view.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L2 copper\u003C/strong>\u003C/td>\n\u003Ctd>Ground copper\u003C/td>\n\u003Ctd>Board fabricator; confirm layer position, net assignment and via clearances.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L3 copper\u003C/strong>\u003C/td>\n\u003Ctd>Power and/or signal copper\u003C/td>\n\u003Ctd>Board fabricator; specify the actual function and confirm it is not confused with L2.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L4 bottom copper\u003C/strong>\u003C/td>\n\u003Ctd>Bottom pads and signal copper\u003C/td>\n\u003Ctd>Board fabricator; confirm layer position and orientation against the other files.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Top and bottom mask\u003C/strong>\u003C/td>\n\u003Ctd>Areas where solder mask is to be opened\u003C/td>\n\u003Ctd>Board fabricator; check that the files correspond to the correct sides and intended exposed features.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Top and bottom legend\u003C/strong>\u003C/td>\n\u003Ctd>Component and other printed identification\u003C/td>\n\u003Ctd>Board fabricator; identify any side with no legend and check for conflicts with openings.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Top and/or bottom paste\u003C/strong>\u003C/td>\n\u003Ctd>Proposed stencil aperture information\u003C/td>\n\u003Ctd>Assembly or stencil recipient; identify applicable sides and review aperture requirements. It is not an additional copper layer.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Board outline\u003C/strong>\u003C/td>\n\u003Ctd>Finished perimeter and relevant routed features\u003C/td>\n\u003Ctd>Board fabricator; make the intended contour unambiguous and distinguish it from other mechanical lines.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Drill and slot information\u003C/strong>\u003C/td>\n\u003Ctd>Hole locations and applicable hole types\u003C/td>\n\u003Ctd>Board fabricator; identify plated and non-plated requirements and any special via endpoints.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Stackup and fabrication drawing\u003C/strong>\u003C/td>\n\u003Ctd>Copper order, construction requirements and supporting notes\u003C/td>\n\u003Ctd>Board fabricator; reconcile these documents with the artwork and any controlled-impedance requirements.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The table is not a substitute for a complete fabrication or assembly package. For example, the outline identifies the shape, but hole tolerances, finished thickness, surface finish and other requirements may need separate specification. The \u003Ca href=\"/en/blog/fab-drawing-essentials\">fabrication drawing essentials\u003C/a> article provides a starting point for that handoff.\u003C/p>\n\u003Ch2 id=\"what-a-cross-section-canand-cannotshow\" data-anchor-en=\"what-a-cross-section-canand-cannotshow\">What a cross-section can—and cannot—show\u003C/h2>\n\u003Cimg src=\"/assets/img/blogs/2026/11/nasa-layer-section-reference.png\" alt=\"NASA coupon through-hole microsection with original arrows indicating missing annular rings\">\n\n\u003Cp>\u003Cem>NASA/GSFC coupon through-hole microsection by Charles E. Powers, 2009. The original arrows indicate missing annular rings. No scale is provided; this image does not establish the board’s total layer count, acceptance status or any APTPCB work. \u003Ca href=\"/assets/credits/nasa-coupon-inspection-credit.txt\">Image credit and source record\u003C/a>.\u003C/em>\u003C/p>\n\u003Cp>A microsection shows a cut through a particular region of a board or coupon. It can help an inspector examine features visible at that location, but this image is not a general layer-count diagram. In particular, the absence of a visible feature at one cut location should not be used to reconstruct the whole board or determine acceptance without the applicable design and inspection criteria.\u003C/p>\n\u003Ch2 id=\"example-a-reversed-or-misnamed-layer-package\" data-anchor-en=\"example-a-reversed-or-misnamed-layer-package\">Example: a reversed or misnamed layer package\u003C/h2>\n\u003Cp>\u003Cstrong>Invented review scenario:\u003C/strong> A purchaser receives a four-layer package with files named \u003Ccode>L1-top\u003C/code>, \u003Ccode>L2-ground\u003C/code>, \u003Ccode>L3-power\u003C/code> and \u003Ccode>L4-bottom\u003C/code>. The drawing also says four copper layers, but a review suggests that the file named \u003Ccode>L1-top\u003C/code> contains the pattern expected on the bottom.\u003C/p>\n\u003Cp>Do not resolve that conflict by trusting the file name, the viewing color or a single screenshot. Colors and display conventions are not universal, and a bottom-side view can appear different depending on how it is presented.\u003C/p>\n\u003Cp>A practical review is:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Hold the release and identify the reference view.\u003C/strong> Ask the designer which side is considered the top and how the artwork is intended to be viewed. Do not assume a file needs mirroring merely because it looks reversed in a viewer.\u003C/li>\n\u003Cli>\u003Cstrong>Compare distinctive features across outputs.\u003C/strong> Check an unambiguous connector, keyed feature or component pad pattern against the intended top and bottom copper, mask, legend and assembly information. Check alignment with the outline and drill locations.\u003C/li>\n\u003Cli>\u003Cstrong>Verify the inner copper order separately.\u003C/strong> A correctly identified top file does not prove that L2 and L3 are in the right order. Compare the layer list and stackup with the actual copper content and intended nets.\u003C/li>\n\u003Cli>\u003Cstrong>Resolve electrical consequences.\u003C/strong> If an inner layer appears mislabeled, check via connections and clearances against the design intent. Simply swapping two file names could create incorrect connections or invalidate the intended reference arrangement.\u003C/li>\n\u003Cli>\u003Cstrong>Issue a corrected package.\u003C/strong> Have the design owner identify the authoritative files and layer order, revise the conflicting output or documentation, and communicate the new revision to every recipient. Remove or clearly supersede the earlier package.\u003C/li>\n\u003C/ol>\n\u003Cp>If the designer cannot establish which output is authoritative, stop and request clarification before fabrication. A board can have the correct number of copper layers and still be wrong because the artwork, order or connectivity was miscommunicated.\u003C/p>\n\u003Ch2 id=\"before-requesting-fabrication\" data-anchor-en=\"before-requesting-fabrication\">Before requesting fabrication\u003C/h2>\n\u003Cp>For an efficient review with APTPCB, identify the copper count and provide the files together with a layer map, stackup requirements and fabrication notes. State any features that need special agreement, such as controlled impedance or non-through vias. For assembly, separately identify paste and other assembly outputs and their intended recipients.\u003C/p>\n\u003Cp>If the package is ready, use the \u003Ca href=\"/en/quote\">quote request\u003C/a>. If the layer mapping or requirements are uncertain, \u003Ca href=\"/en/contact\">contact APTPCB\u003C/a> before treating the files as released.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch3 id=\"public-source-references\" data-anchor-en=\"public-source-references\">Public source references\u003C/h3>\n\u003Cul>\n\u003Cli>KiCad, \u003Cem>Pcbnew Layers\u003C/em>.\u003C/li>\n\u003Cli>NASA, PCB fabrication presentation, NASA Technical Reports Server record 20190001381.\u003C/li>\n\u003Cli>NASA/GSFC, Charles E. Powers, 2009 coupon inspection image, NASA Technical Reports Server record 20090027819; see the linked image credit and source record above.\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/what-is-a-pcb\">what is a PCB\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-stackup-design\">PCB stackup design\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/what-is-solder-mask\">what is solder mask\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/fab-drawing-essentials\">fabrication drawing essentials\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">quote request\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact APTPCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32],{"id":15,"text":16},"copper-count-versus-physical-construction","Copper count versus physical construction",{"id":18,"text":19},"a-hypothetical-four-copper-layer-example","A hypothetical four-copper-layer example",{"id":21,"text":22},"mask-legend-and-paste-different-jobs","Mask, legend and paste: different jobs",{"id":24,"text":25},"map-each-file-to-its-recipient","Map each file to its recipient",{"id":27,"text":28},"what-a-cross-section-canand-cannotshow","What a cross-section can—and cannot—show",{"id":30,"text":31},"example-a-reversed-or-misnamed-layer-package","Example: a reversed or misnamed layer package",{"id":33,"text":34},"before-requesting-fabrication","Before requesting fabrication",[36,37,38],"PCB layers","copper layers","PCB stackup","pcb-layers-explained",{"blog":41,"breadcrumb":50,"faq":64},{"@context":42,"@type":43,"headline":4,"description":5,"image":8,"url":44,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":45,"articleSection":7,"author":46,"publisher":49},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/pcb-layers-explained","PCB layers, copper layers, PCB stackup",{"@type":47,"name":48},"Organization","APTPCB",{"@type":47,"name":48},{"@context":42,"@type":51,"itemListElement":52},"BreadcrumbList",[53,58,62],{"@type":54,"position":55,"name":56,"item":57},"ListItem",1,"Home","https://aptpcb.com/",{"@type":54,"position":59,"name":60,"item":61},2,"Blog","https://aptpcb.com/en/blog",{"@type":54,"position":63,"name":39,"item":44},3,null,{"pcbManufacturingColumns":66,"capabilityColumns":194,"resourceColumns":230,"pcbaColumns":274},[67,115,144,173],{"heading":68,"links":69},"PCB Product Families",[70,73,76,79,82,85,88,91,94,97,100,103,106,109,112],{"label":71,"path":72},"FR-4 PCB","/pcb/fr4-pcb",{"label":74,"path":75},"High-Speed PCB","/pcb/high-speed-pcb",{"label":77,"path":78},"Multilayer PCB","/pcb/multilayer-pcb",{"label":80,"path":81},"HDI PCB","/pcb/hdi-pcb",{"label":83,"path":84},"Flexible PCB","/pcb/flex-pcb",{"label":86,"path":87},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":89,"path":90},"Ceramic PCB","/pcb/ceramic-pcb",{"label":92,"path":93},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":95,"path":96},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":98,"path":99},"Antenna PCB","/pcb/antenna-pcb",{"label":101,"path":102},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":104,"path":105},"Microwave PCB","/pcb/microwave-pcb",{"label":107,"path":108},"Metal Core PCB","/pcb/metal-core-pcb",{"label":110,"path":111},"High-Tg PCB","/pcb/high-tg-pcb",{"label":113,"path":114},"Backplane PCB","/pcb/backplane-pcb",{"sections":116},[117],{"heading":118,"links":119},"RF & Materials",[120,123,126,129,132,135,138,141],{"label":121,"path":122},"Rogers PCB","/materials/rf-rogers",{"label":124,"path":125},"Taconic PCB","/materials/taconic-pcb",{"label":127,"path":128},"Teflon PCB","/materials/teflon-pcb",{"label":130,"path":131},"Arlon PCB","/materials/arlon-pcb",{"label":133,"path":134},"Megtron PCB","/materials/megtron-pcb",{"label":136,"path":137},"ISOLA PCB","/materials/isola-pcb",{"label":139,"path":140},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":142,"path":143},"Impedance Control","/pcb/pcb-impedance-control",{"sections":145},[146],{"heading":147,"links":148},"Manufacturing / Stackups",[149,152,155,158,161,164,167,170],{"label":150,"path":151},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":153,"path":154},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":156,"path":157},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":159,"path":160},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":162,"path":163},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":165,"path":166},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":168,"path":169},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":171,"path":172},"Multi-Layer Laminated Structure","/pcb/multilayer-pcb-lamination-services",{"heading":174,"links":175},"Specialties & Resources",[176,179,182,185,188,191],{"label":177,"path":178},"PCB Design & Layout Services","/pcba/pcb-design-services",{"label":180,"path":181},"PCB Surface Finishes","/pcb/pcb-surface-finishes",{"label":183,"path":184},"PCB Drilling & Vias","/pcb/pcb-drilling",{"label":186,"path":187},"PCB Stackup","/pcb/pcb-stack-up",{"label":189,"path":190},"PCB Profiling","/pcb/pcb-profiling",{"label":192,"path":193},"Quality & Inspection","/pcb/pcb-quality",[195,200,205,210,215,220,225],{"links":196},[197],{"label":198,"path":199},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":201},[202],{"label":203,"path":204},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":206},[207],{"label":208,"path":209},"Flex PCB Capability","/capabilities/flex-pcb",{"links":211},[212],{"label":213,"path":214},"HDI PCB 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