[{"data":1,"prerenderedAt":405},["ShallowReactive",2],{"blog-pcb-routing-guidelines-en":3,"header-nav-en":69},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":38,"slug":43,"jsonld":44},"PCB routing guidelines: constraints, return paths and fabrication handoff","Plan PCB routing around electrical constraints, return paths, layer transitions and manufacturing requirements.","2026-11-08","design","/assets/img/blogs/2026/09/pcb-routing-layout-example.png",11,2075,"PT11M","\u003Cp>Route a PCB by first identifying the nets and current loops that have the least flexibility, then set their electrical and manufacturing constraints before filling in the remaining connections. Review each important route as a complete path: conductor, reference plane, layer transitions, return current and connections at both ends.\u003C/p>\n\u003Cp>There is no universal routing order. A high-speed interface, a converter switching loop or a high-current path may take priority depending on the design. The useful question is which layout decisions are hardest to change later and most consequential if they are wrong.\u003C/p>\n\u003Cp>Placement and schematic decisions also shape the available routes; see the \u003Ca href=\"/en/blog/pcb-design-guide\">PCB design guide\u003C/a> for those broader steps.\u003C/p>\n\u003Ch2 id=\"set-constraints-before-drawing-tracks\" data-anchor-en=\"set-constraints-before-drawing-tracks\">Set constraints before drawing tracks\u003C/h2>\n\u003Cp>A routing constraint should have a source and an owner. Device documentation, interface requirements, circuit analysis and the intended stackup all contribute electrical requirements. The selected fabrication process contributes manufacturing constraints. Resolve conflicts before treating a layout rule as approved.\u003C/p>\n\u003Cp>Start with these inputs:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Stackup and reference planes.\u003C/strong> Identify the copper layers, their intended functions and the reference available to critical signals. A layer change is also a change in the signal’s electromagnetic environment and may require a return-current transition.\u003C/li>\n\u003Cli>\u003Cstrong>Signal requirements.\u003C/strong> Identify nets with impedance, timing, topology, matching or noise constraints. Use the requirements of the actual interface and devices rather than assuming every fast-looking net needs the same treatment.\u003C/li>\n\u003Cli>\u003Cstrong>Power and thermal conditions.\u003C/strong> Determine current paths and their expected operating conditions. Width, copper thickness, temperature rise, surrounding copper and layer transitions all influence the result.\u003C/li>\n\u003Cli>\u003Cstrong>Voltage and isolation needs.\u003C/strong> Set spacing and other isolation requirements from the applicable product requirements and operating environment, not a generic routing rule.\u003C/li>\n\u003Cli>\u003Cstrong>Fabrication constraints.\u003C/strong> Confirm achievable trace, space, drill and copper features for the proposed design. A default CAD rule is not evidence that the selected board can be made as specified.\u003C/li>\n\u003C/ul>\n\u003Cp>Assign these requirements to net classes, individual nets, regions or layer-specific rules as appropriate in the layout tool. Record exceptions and their reasons. If a constraint is still provisional, mark it for resolution rather than silently relying on it.\u003C/p>\n\u003Cp>For a closer look at the layer decisions behind routing, see \u003Ca href=\"/en/blog/pcb-stackup-design\">PCB stackup design\u003C/a>.\u003C/p>\n\u003Ch2 id=\"choose-routing-priorities-around-the-designs-risks\" data-anchor-en=\"choose-routing-priorities-around-the-designs-risks\">Choose routing priorities around the design’s risks\u003C/h2>\n\u003Cp>Routing priority is best established alongside placement. A path that requires a short loop, a particular topology or an uninterrupted reference may depend on component locations more than on the route itself. If those locations make the requirement impractical, revisit placement before adding detours.\u003C/p>\n\u003Cp>A practical sequence is to identify the constrained structures, reserve the space and references they need, and then route the less constrained connections around them. The constrained structures might include:\u003C/p>\n\u003Cul>\n\u003Cli>A converter’s switching and input-current loops, where component placement and loop area matter.\u003C/li>\n\u003Cli>A high-speed link whose topology, reference continuity or impedance is specified.\u003C/li>\n\u003Cli>A high-current path whose conductor and via arrangement must suit the electrical and thermal conditions.\u003C/li>\n\u003Cli>A sensitive analog input that needs separation from an identified noise source.\u003C/li>\n\u003Cli>A connector escape where pin assignments and available layers restrict routing options.\u003C/li>\n\u003C/ul>\n\u003Cp>These are candidates for early attention, not a ranked list. For example, a converter loop may dictate local placement while a memory interface dictates a larger routing region. Both can need early planning, even if one is physically routed first.\u003C/p>\n\u003Cp>Avoid judging success solely by the shortest visible trace. A longer route over a continuous reference may be preferable to a shorter route across a gap. Conversely, an unnecessary detour can add delay, coupling or congestion. Evaluate the route against its actual constraints.\u003C/p>\n\u003Ch2 id=\"routing-review-matrix\" data-anchor-en=\"routing-review-matrix\">Routing review matrix\u003C/h2>\n\u003Cp>During layout review, distinguish a checked requirement from a rule that merely exists in the CAD database.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Routing decision\u003C/th>\n\u003Cth>Constraint to establish\u003C/th>\n\u003Cth>Review question\u003C/th>\n\u003Cth>Evidence to retain\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Priority and placement\u003C/td>\n\u003Ctd>Critical loops, topology and reserved routing regions\u003C/td>\n\u003Ctd>Can each critical path be routed without compromising its source, load or reference?\u003C/td>\n\u003Ctd>Net list, placement review and identified critical paths\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Signal layer and reference\u003C/td>\n\u003Ctd>Intended reference conductor for each critical route\u003C/td>\n\u003Ctd>Does the route remain over an appropriate continuous reference, including near connectors and voids?\u003C/td>\n\u003Ctd>Stackup and layout views showing signal and reference layers\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Layer transition\u003C/td>\n\u003Ctd>Signal-via geometry and return-current path\u003C/td>\n\u003Ctd>How does return current move between references, and does that transition suit the circuit?\u003C/td>\n\u003Ctd>Via and plane-region review, with design rationale\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Controlled impedance\u003C/td>\n\u003Ctd>Target, tolerance, geometry and stackup assumptions\u003C/td>\n\u003Ctd>Does the proposed geometry correspond to the specified layer and reference?\u003C/td>\n\u003Ctd>Impedance requirements and agreed stackup or fabrication feedback\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Power and high-current routing\u003C/td>\n\u003Ctd>Current, copper, thermal conditions and voltage requirements\u003C/td>\n\u003Ctd>Are traces, planes, neck-downs and vias appropriate for the expected path?\u003C/td>\n\u003Ctd>Current and thermal assumptions, calculations or engineering review\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Sensitive and noisy circuits\u003C/td>\n\u003Ctd>Noise sources, coupling paths and device-specific grounding needs\u003C/td>\n\u003Ctd>Could switching current or a nearby aggressor disturb the sensitive path?\u003C/td>\n\u003Ctd>Component guidance and layout review of the relevant region\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Manufacturing handoff\u003C/td>\n\u003Ctd>Fabrication rules, files and acceptance requirements\u003C/td>\n\u003Ctd>Do the released outputs describe the same revision and constraints used for review?\u003C/td>\n\u003Ctd>Output checks, netlist comparison and fabrication notes\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>A completed matrix is not a substitute for analysis or testing. Its value is making the assumptions and unresolved questions visible before the design is released.\u003C/p>\n\u003Ch2 id=\"preserve-the-return-path\" data-anchor-en=\"preserve-the-return-path\">Preserve the return path\u003C/h2>\n\u003Cp>Every signal is part of a circuit: current leaves a source and returns through a path determined by the conductors and impedances available. For fast edges, return current tends to follow a nearby low-impedance reference path. If a route crosses a gap or reference discontinuity, the return path may have to detour, increasing loop area and potentially worsening coupling or emissions.\u003C/p>\n\u003Cp>Review the reference under the entire route, not just the signal layer in isolation. Look for plane splits, copper voids, cutouts, antipads and connector regions that interrupt the intended path. A route can pass a spacing check while still crossing a poor reference region.\u003C/p>\n\u003Cp>When a signal changes layers, check both sides of the transition:\u003C/p>\n\u003Col>\n\u003Cli>Identify the reference for the incoming route and the reference for the outgoing route.\u003C/li>\n\u003Cli>Check whether the references are continuous or connected in a way that supports the return current.\u003C/li>\n\u003Cli>Review the signal via and nearby structures in the context of the stackup and circuit.\u003C/li>\n\u003Cli>If the return transition is unclear, consider changing the route, layer assignment or plane arrangement.\u003C/li>\n\u003C/ol>\n\u003Cp>Ground vias can provide a connection between ground references when appropriate. Where the references are different nets, the return transition may depend on the circuit and its power-distribution design; do not assume that a ground via alone resolves it. The right solution depends on the actual reference planes and device requirements.\u003C/p>\n\u003Cp>\u003Cstrong>Hypothetical example:\u003C/strong> A fast signal moves from a layer referenced to a ground plane to another layer referenced to a different ground plane. The signal via connects the trace segments, but it does not by itself connect the two reference planes. The designer reviews the plane geometry and provides an appropriate nearby ground connection if the design supports it, then checks that the route does not encounter a void at the transition. If the outgoing layer instead references a power plane, the return transition needs a separate circuit-specific review.\u003C/p>\n\u003Cp>A ground split is not automatically an improvement, and a fixed number of stitching vias is not a universal remedy. TI’s High-Speed Layout Guidelines and Analog Devices’ guidance on mixed-signal PCB layout are useful primary references for understanding return paths and grounding choices. Apply device-specific documentation where it gives more direct requirements.\u003C/p>\n\u003Ch2 id=\"route-power-and-sensitive-signals-in-context\" data-anchor-en=\"route-power-and-sensitive-signals-in-context\">Route power and sensitive signals in context\u003C/h2>\n\u003Cp>For power paths, trace width is only one part of the problem. Check the full path through connectors, pads, neck-downs, vias, planes and returns. A wide section does not compensate for an overlooked bottleneck elsewhere. Consider the expected current, copper thickness, thermal environment and any relevant transient behavior when selecting geometry.\u003C/p>\n\u003Cp>Switching converters need particular attention to the loops carrying rapidly changing current. Component placement, local connections and the relationship between power and control circuitry can be more important than making a distant power trace visually neat. TI’s Layout Optimization of 4-Switch Buck-Boost Converters illustrates why converter layout must follow the circuit’s operating behavior rather than a generic grounding pattern.\u003C/p>\n\u003Cp>For sensitive analog signals, identify the likely aggressors and coupling mechanisms before imposing separation rules. A switching node, a high-current return or a fast digital route can affect a sensitive input differently. Review where their current flows and whether shared impedance, capacitive coupling or magnetic coupling is plausible.\u003C/p>\n\u003Cp>Keep grounding decisions tied to the devices and signal paths. Automatically separating analog and digital ground into disconnected regions can create return-path problems if signals must cross the boundary. Where a device specifies a grounding or placement arrangement, evaluate it against the complete board and the intended current paths.\u003C/p>\n\u003Ch2 id=\"verify-vias-and-controlled-impedance\" data-anchor-en=\"verify-vias-and-controlled-impedance\">Verify vias and controlled impedance\u003C/h2>\n\u003Cp>A via is more than a connection between two copper layers. For a critical signal, review its position relative to the route, reference planes and other vias. Check the effect of the transition on the signal path and on return current. For power, evaluate the current path and thermal assumptions through the via arrangement as well as the copper on each side.\u003C/p>\n\u003Cp>For controlled-impedance routes, provide the target and tolerance together with the applicable nets or structures, layers, stackup and reference assumptions. Trace width and spacing alone do not define impedance independently of the surrounding geometry and materials. Differential routes also need the topology and coupling requirements appropriate to the interface; visual symmetry alone is not verification.\u003C/p>\n\u003Cp>The layout tool’s impedance settings are useful only when their inputs correspond to the intended fabrication stackup. Ask the fabricator to confirm the stackup and proposed impedance approach for the project before treating the geometry as settled. See \u003Ca href=\"/en/blog/impedance-controlled-pcb\">controlled-impedance PCB design\u003C/a> and \u003Ca href=\"/en/blog/high-speed-pcb-design\">high-speed PCB design\u003C/a> for related design considerations.\u003C/p>\n\u003Cp>Do not use a fixed bend angle or a generic trace-spacing multiple as proof of signal integrity. Those choices may be useful layout conventions in some situations, but they do not replace analysis of the actual route, coupling and interface requirements.\u003C/p>\n\u003Ch2 id=\"review-the-routed-board-before-release\" data-anchor-en=\"review-the-routed-board-before-release\">Review the routed board before release\u003C/h2>\n\u003Cp>Run design-rule checks against the current constraint set, then review what those checks cannot establish. DRC can flag many geometry and connectivity problems, but it does not by itself validate return-current behavior, electromagnetic compatibility or circuit function.\u003C/p>\n\u003Cp>A routing review should include:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Connectivity:\u003C/strong> Compare the layout against the intended netlist and investigate unresolved or unintended connections.\u003C/li>\n\u003Cli>\u003Cstrong>Critical paths:\u003C/strong> Inspect complete routes, including pads, vias, reference changes and nearby discontinuities.\u003C/li>\n\u003Cli>\u003Cstrong>Power paths:\u003C/strong> Check current-carrying features and bottlenecks against documented assumptions.\u003C/li>\n\u003Cli>\u003Cstrong>Constraint coverage:\u003C/strong> Confirm that critical nets have the intended rules and that exceptions are reviewed.\u003C/li>\n\u003Cli>\u003Cstrong>Fabrication geometry:\u003C/strong> Check the proposed features against the project’s confirmed manufacturing constraints.\u003C/li>\n\u003Cli>\u003Cstrong>Output consistency:\u003C/strong> Confirm that fabrication files, drill information, stackup and notes describe the same board revision.\u003C/li>\n\u003C/ul>\n\u003Cp>Where the product requires analysis or testing, define that work explicitly. Fabricating or assembling a board is not the same as qualifying a finished system. Board-level checks may support a qualification plan, but they do not establish system performance on their own.\u003C/p>\n\u003Ch2 id=\"prepare-the-fabrication-rfq\" data-anchor-en=\"prepare-the-fabrication-rfq\">Prepare the fabrication RFQ\u003C/h2>\n\u003Cp>A clear RFQ lets the fabricator evaluate the design that is actually intended for release. Provide revision-controlled information and identify any assumptions that remain open:\u003C/p>\n\u003Cul>\n\u003Cli>Fabrication data for the board revision, including relevant layer and outline information.\u003C/li>\n\u003Cli>Drill data and a netlist for the same revision.\u003C/li>\n\u003Cli>The proposed stackup, copper requirements and any layer-specific constraints.\u003C/li>\n\u003Cli>Controlled-impedance targets and tolerances, with the applicable structures or nets, where required.\u003C/li>\n\u003Cli>Required quantities.\u003C/li>\n\u003Cli>Relevant acceptance criteria and test requirements, including any required documentation or deliverables.\u003C/li>\n\u003C/ul>\n\u003Cp>Check that the files and notes agree. For example, a controlled-impedance note should identify the structures to which it applies and be consistent with the stackup sent with the RFQ. If a feature or requirement is provisional, say so and ask for it to be reviewed rather than leaving the fabricator to infer intent.\u003C/p>\n\u003Cp>When requesting a quote from APTPCB, ask it to confirm project feasibility and clarify the scope of its review and deliverables for your supplied requirements. You can use the \u003Ca href=\"/en/quote\">quote page\u003C/a> or \u003Ca href=\"/en/contact\">contact APTPCB\u003C/a> to discuss the handoff.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/pcb-design-guide\">PCB design guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-stackup-design\">PCB stackup design\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/impedance-controlled-pcb\">controlled-impedance PCB design\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/high-speed-pcb-design\">high-speed PCB design\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">quote page\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact APTPCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32,35],{"id":15,"text":16},"set-constraints-before-drawing-tracks","Set constraints before drawing tracks",{"id":18,"text":19},"choose-routing-priorities-around-the-designs-risks","Choose routing priorities around the design’s risks",{"id":21,"text":22},"routing-review-matrix","Routing review matrix",{"id":24,"text":25},"preserve-the-return-path","Preserve the return path",{"id":27,"text":28},"route-power-and-sensitive-signals-in-context","Route power and sensitive signals in context",{"id":30,"text":31},"verify-vias-and-controlled-impedance","Verify vias and controlled impedance",{"id":33,"text":34},"review-the-routed-board-before-release","Review the routed board before release",{"id":36,"text":37},"prepare-the-fabrication-rfq","Prepare the fabrication RFQ",[39,40,41,42],"PCB routing guidelines","PCB layout","return paths","PCB fabrication","pcb-routing-guidelines",{"blog":45,"breadcrumb":54,"faq":68},{"@context":46,"@type":47,"headline":4,"description":5,"image":8,"url":48,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":49,"articleSection":7,"author":50,"publisher":53},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/pcb-routing-guidelines","PCB routing guidelines, PCB layout, return paths, PCB fabrication",{"@type":51,"name":52},"Organization","APTPCB",{"@type":51,"name":52},{"@context":46,"@type":55,"itemListElement":56},"BreadcrumbList",[57,62,66],{"@type":58,"position":59,"name":60,"item":61},"ListItem",1,"Home","https://aptpcb.com/",{"@type":58,"position":63,"name":64,"item":65},2,"Blog","https://aptpcb.com/en/blog",{"@type":58,"position":67,"name":43,"item":48},3,null,{"pcbManufacturingColumns":70,"capabilityColumns":198,"resourceColumns":234,"pcbaColumns":278},[71,119,148,177],{"heading":72,"links":73},"PCB Product Families",[74,77,80,83,86,89,92,95,98,101,104,107,110,113,116],{"label":75,"path":76},"FR-4 PCB","/pcb/fr4-pcb",{"label":78,"path":79},"High-Speed PCB","/pcb/high-speed-pcb",{"label":81,"path":82},"Multilayer PCB","/pcb/multilayer-pcb",{"label":84,"path":85},"HDI PCB","/pcb/hdi-pcb",{"label":87,"path":88},"Flexible PCB","/pcb/flex-pcb",{"label":90,"path":91},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":93,"path":94},"Ceramic PCB","/pcb/ceramic-pcb",{"label":96,"path":97},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":99,"path":100},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":102,"path":103},"Antenna PCB","/pcb/antenna-pcb",{"label":105,"path":106},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":108,"path":109},"Microwave PCB","/pcb/microwave-pcb",{"label":111,"path":112},"Metal Core PCB","/pcb/metal-core-pcb",{"label":114,"path":115},"High-Tg PCB","/pcb/high-tg-pcb",{"label":117,"path":118},"Backplane PCB","/pcb/backplane-pcb",{"sections":120},[121],{"heading":122,"links":123},"RF & Materials",[124,127,130,133,136,139,142,145],{"label":125,"path":126},"Rogers PCB","/materials/rf-rogers",{"label":128,"path":129},"Taconic PCB","/materials/taconic-pcb",{"label":131,"path":132},"Teflon PCB","/materials/teflon-pcb",{"label":134,"path":135},"Arlon PCB","/materials/arlon-pcb",{"label":137,"path":138},"Megtron PCB","/materials/megtron-pcb",{"label":140,"path":141},"ISOLA PCB","/materials/isola-pcb",{"label":143,"path":144},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":146,"path":147},"Impedance Control","/pcb/pcb-impedance-control",{"sections":149},[150],{"heading":151,"links":152},"Manufacturing / Stackups",[153,156,159,162,165,168,171,174],{"label":154,"path":155},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":157,"path":158},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":160,"path":161},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":163,"path":164},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":166,"path":167},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":169,"path":170},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":172,"path":173},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":175,"path":176},"Multi-Layer Laminated Structure","/pcb/multilayer-pcb-lamination-services",{"heading":178,"links":179},"Specialties & Resources",[180,183,186,189,192,195],{"label":181,"path":182},"PCB Design & Layout Services","/pcba/pcb-design-services",{"label":184,"path":185},"PCB Surface Finishes","/pcb/pcb-surface-finishes",{"label":187,"path":188},"PCB Drilling & Vias","/pcb/pcb-drilling",{"label":190,"path":191},"PCB Stackup","/pcb/pcb-stack-up",{"label":193,"path":194},"PCB Profiling","/pcb/pcb-profiling",{"label":196,"path":197},"Quality & Inspection","/pcb/pcb-quality",[199,204,209,214,219,224,229],{"links":200},[201],{"label":202,"path":203},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":205},[206],{"label":207,"path":208},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":210},[211],{"label":212,"path":213},"Flex PCB Capability","/capabilities/flex-pcb",{"links":215},[216],{"label":217,"path":218},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":220},[221],{"label":222,"path":223},"Metal PCB Capability","/capabilities/metal-pcb",{"links":225},[226],{"label":227,"path":228},"Ceramic PCB Capability","/capabilities/ceramic-pcb",{"links":230},[231],{"label":232,"path":233},"Heavy Copper PCB Capability","/capabilities/heavy-copper-pcb",[235,246,270],{"heading":236,"links":237},"Downloads",[238,241,244],{"label":239,"path":240},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":242,"path":243},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":175,"path":245},"/pcb/multi-layer-laminated-structure",{"heading":247,"links":248},"Tools",[249,252,255,258,261,264,267],{"label":250,"path":251},"Gerber Viewer","/tools/gerber-viewer",{"label":253,"path":254},"PCB Viewer","/tools/pcb-viewer",{"label":256,"path":257},"BOM Viewer","/tools/bom-viewer",{"label":259,"path":260},"3D Viewer","/tools/3d-viewer",{"label":262,"path":263},"Circuit Simulator","/tools/circuit-simulator",{"label":265,"path":266},"Impedance Calculator","/tools/impedance-calculator",{"label":268,"path":269},"Trace Width Calculator","/tools/trace-width-calculator",{"heading":271,"links":272},"FAQ & Blog",[273,276],{"label":274,"path":275},"FAQ","/resources/faq",{"label":64,"path":277},"/blog",[279,309,335,368],{"heading":280,"links":281},"Core Services",[282,285,288,291,294,297,300,303,306],{"label":283,"path":284},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":286,"path":287},"NPI & Small Batch PCB Assembly","/pcba/npi-assembly",{"label":289,"path":290},"Mass Production PCB Assembly","/pcba/mass-production",{"label":292,"path":293},"Flex & Rigid-Flex PCB Assembly","/pcba/flex-rigid-flex",{"label":295,"path":296},"SMT & Through-Hole Assembly","/pcba/smt-tht",{"label":298,"path":299},"BGA PCB Assembly","/pcba/bga-qfn-fine-pitch",{"label":301,"path":302},"Components & BOM Management","/pcba/components-bom",{"label":304,"path":305},"Box Build Assembly","/pcba/box-build-assembly",{"label":307,"path":308},"PCB Assembly Testing & Quality","/pcba/testing-quality",{"heading":310,"links":311},"Supporting Services",[312,314,317,320,323,326,329,332],{"label":313,"path":182},"PCB Design & Layout",{"label":315,"path":316},"Every Support Touchpoint","/pcba/support-services",{"label":318,"path":319},"Stencil Lab","/pcba/pcb-stencil",{"label":321,"path":322},"Components Sourcing","/pcba/component-sourcing",{"label":324,"path":325},"IC Programming","/pcba/ic-programming",{"label":327,"path":328},"Conformal Coating","/pcba/pcb-conformal-coating",{"label":330,"path":331},"Selective Soldering","/pcba/pcb-selective-soldering",{"label":333,"path":334},"BGA Reballing","/pcba/bga-reballing",{"heading":336,"links":337},"Quality & Testing",[338,341,344,347,350,353,356,359,362,365],{"label":339,"path":340},"Quality Inspection","/pcba/quality-system",{"label":342,"path":343},"First Article Inspection (FAI)","/pcba/first-article-inspection",{"label":345,"path":346},"Solder Paste Inspection (SPI)","/pcba/spi-inspection",{"label":348,"path":349},"AOI Optical Inspection","/pcba/aoi-inspection",{"label":351,"path":352},"X-Ray / CT Inspection","/pcba/xray-inspection",{"label":354,"path":355},"ICT In-Circuit Testing","/pcba/ict-test",{"label":357,"path":358},"Flying Probe Testing","/pcba/flying-probe-testing",{"label":360,"path":361},"FCT / Functional Testing","/pcba/fct-test",{"label":363,"path":364},"Final Inspection & Packing","/pcba/final-quality-inspection",{"label":366,"path":367},"Incoming Quality Control","/pcba/incoming-quality-control",{"heading":369,"linkClass":370,"links":371},"Industry Applications (Entry)","text-nowrap",[372,375,378,381,384,387,390,393,396,399,402],{"label":373,"path":374},"Server / Data Center","/industries/server-data-center-pcb",{"label":376,"path":377},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":379,"path":380},"Medical","/industries/medical-pcb",{"label":382,"path":383},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":385,"path":386},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":388,"path":389},"Drone / UAV","/industries/drone-uav-pcb",{"label":391,"path":392},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":394,"path":395},"Power & New Energy","/industries/power-energy-pcb",{"label":397,"path":398},"Robotics & Automation","/industries/robotics-pcb",{"label":400,"path":401},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":403,"path":404},"PCB Industry Overview →","/pcb-industry-solutions",1794151724675]