[{"data":1,"prerenderedAt":397},["ShallowReactive",2],{"blog-pcba-assembly-test-quality-guide-en":3,"header-nav-en":69},{"title":4,"description":5,"date":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tags":13,"slug":19,"jsonld":20},"PCBA Assembly Test and Quality Guide: Inspection Layers, Test Strategy, and Release Gates","A practical engineering guide to PCBA assembly test and quality: how BOM control, assembly inputs, layered inspection, ICT or flying probe, functional test, and release gates work together before shipment.","2026-05-13","technology","/assets/img/blogs/2026/05/pcba-assembly-test-quality-guide.webp",13,2574,"PT13M","\u003Cul>\n\u003Cli>PCBA assembly quality should be treated as a \u003Cstrong>layered release system\u003C/strong>, not as one vague promise that a board was simply "tested."\u003C/li>\n\u003Cli>The most useful boundary is to separate \u003Cstrong>build inputs\u003C/strong>, \u003Cstrong>inspection layers\u003C/strong>, \u003Cstrong>electrical verification\u003C/strong>, \u003Cstrong>functional behavior\u003C/strong>, and \u003Cstrong>shipment release gates\u003C/strong>.\u003C/li>\n\u003Cli>A board can pass one gate and still fail the next because SPI, AOI, X-ray, ICT, flying probe, FCT, FAI, and final inspection answer different questions.\u003C/li>\n\u003Cli>The safest public framing is to explain which method is responsible for which defect class or release decision, and to avoid implying that every program gets every test layer.\u003C/li>\n\u003C/ul>\n\u003Cblockquote>\n\u003Cp>\u003Cstrong>Quick Answer\u003C/strong>\u003Cbr>PCBA assembly test and quality are easiest to manage when the team reviews the build in order: BOM and component control, assembly definition, inspection stack selection, electrical or functional verification, and final release governance. The better question is not "Was the board tested?" but "Which gate was responsible for catching which risk before shipment?" That framing prevents AOI, X-ray, ICT, flying probe, FCT, FAI, and traceability from being collapsed into one generic claim.\u003C/p>\n\u003C/blockquote>\n\u003Cp>If your program already depends on inspection planning or release evidence, start with \u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>, \u003Ca href=\"/en/pcba/turnkey-assembly\">Turnkey Assembly\u003C/a>, and \u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a> before using this guide to classify the deeper assembly and test burden.\u003C/p>\n\u003Ch2 id=\"table-of-contents\" data-anchor-en=\"table-of-contents\">Table of Contents\u003C/h2>\n\u003Cul>\n\u003Cli>\u003Ca href=\"#what-this-means\">What counts as PCBA assembly test and quality here?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#first-review\">What should engineers review first?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#input-control\">Why assembly input control starts before test\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#method-boundaries\">How inspection and electrical methods divide responsibility\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#release-gates\">Why release gates and traceability stay separate from defect detection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#project-types\">Which project types change the review order?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#freeze-before-release\">What should be frozen before RFQ, first build, or shipment release?\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#next-steps\">Next steps with APTPCB\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#faq\">FAQ\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#references\">Public references\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"#author\">Author and review information\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ca id=\"what-this-means\">\u003C/a>\n\u003Ch2 id=\"what-counts-as-pcba-assembly-test-and-quality-here\" data-anchor-en=\"what-counts-as-pcba-assembly-test-and-quality-here\">What counts as PCBA assembly test and quality here?\u003C/h2>\n\u003Cp>Here, \u003Ccode>PCBA assembly test and quality\u003C/code> means the full board-level control path from \u003Cstrong>build inputs to shipment release\u003C/strong>.\u003C/p>\n\u003Cp>That includes:\u003C/p>\n\u003Cul>\n\u003Cli>BOM and component sourcing control\u003C/li>\n\u003Cli>assembly drawing and process-definition clarity\u003C/li>\n\u003Cli>incoming quality checks\u003C/li>\n\u003Cli>SPI, AOI, and X-ray where the build requires them\u003C/li>\n\u003Cli>ICT or flying probe for electrical defect screening\u003C/li>\n\u003Cli>FCT for powered behavior validation\u003C/li>\n\u003Cli>FAI, final inspection, traceability, and release documentation\u003C/li>\n\u003C/ul>\n\u003Cp>Those layers belong together, but they should not be treated as interchangeable.\u003C/p>\n\u003Cp>The common mistake is to write as if:\u003C/p>\n\u003Col>\n\u003Cli>inspection means the same thing as testing\u003C/li>\n\u003Cli>electrical test means the same thing as functional proof\u003C/li>\n\u003Cli>traceability means the same thing as quality assurance\u003C/li>\n\u003Cli>final inspection means the same thing as zero-defect release\u003C/li>\n\u003C/ol>\n\u003Cp>Those are not the same decisions.\u003C/p>\n\u003Cp>The better question is:\u003C/p>\n\u003Cp>\u003Cstrong>Which quality layer owns which risk, and what evidence is still needed before the board can be released?\u003C/strong>\u003C/p>\n\u003Ca id=\"first-review\">\u003C/a>\n\u003Ch2 id=\"what-should-engineers-review-first\" data-anchor-en=\"what-should-engineers-review-first\">What should engineers review first?\u003C/h2>\n\u003Cp>Start with these five boundaries:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>build-input control\u003C/strong>\u003C/li>\n\u003Cli>\u003Cstrong>inspection-layer selection\u003C/strong>\u003C/li>\n\u003Cli>\u003Cstrong>electrical versus functional verification\u003C/strong>\u003C/li>\n\u003Cli>\u003Cstrong>release-gate governance\u003C/strong>\u003C/li>\n\u003Cli>\u003Cstrong>evidence boundary\u003C/strong>\u003C/li>\n\u003C/ol>\n\u003Cp>That order matters because many assembly problems appear before the first powered test ever begins.\u003C/p>\n\u003Cp>The first engineering questions are usually:\u003C/p>\n\u003Cul>\n\u003Cli>Is the BOM stable enough and traceable enough to support the intended build?\u003C/li>\n\u003Cli>Does the assembly package define placement, polarity, mixed-process handling, and reflow assumptions clearly enough?\u003C/li>\n\u003Cli>Which defects need optical inspection, which need hidden-joint inspection, and which need electrical verification?\u003C/li>\n\u003Cli>Is this build better suited to fixture-based ICT or fixture-free flying probe?\u003C/li>\n\u003Cli>Does the customer need powered functional proof, or only manufacturing-defect screening plus release inspection?\u003C/li>\n\u003C/ul>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Review boundary\u003C/th>\n\u003Cth>What it answers\u003C/th>\n\u003Cth>What it does not prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Build inputs\u003C/td>\n\u003Ctd>Whether the board can be assembled from the intended materials and instructions\u003C/td>\n\u003Ctd>That the assembled board will pass electrical or functional validation\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Inspection layers\u003C/td>\n\u003Ctd>Whether visible or hidden assembly defects can be screened at the right stage\u003C/td>\n\u003Ctd>End-use behavior in the target system\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Electrical verification\u003C/td>\n\u003Ctd>Whether opens, shorts, polarity issues, or component-level faults are being screened\u003C/td>\n\u003Ctd>Full powered functionality or field reliability\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Release governance\u003C/td>\n\u003Ctd>Whether incoming, first-article, final inspection, and traceability gates are complete\u003C/td>\n\u003Ctd>That any one gate can replace the rest\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Evidence boundary\u003C/td>\n\u003Ctd>Which claims the board-level package can support before shipment\u003C/td>\n\u003Ctd>System qualification, compliance, or lifetime proof by default\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ca id=\"input-control\">\u003C/a>\n\u003Ch2 id=\"why-assembly-input-control-starts-before-test\" data-anchor-en=\"why-assembly-input-control-starts-before-test\">Why assembly input control starts before test\u003C/h2>\n\u003Cp>PCBA quality starts upstream of AOI, ICT, or FCT.\u003C/p>\n\u003Cp>If the BOM, assembly instructions, and process assumptions are weak, later test stages are forced to diagnose problems that were created much earlier.\u003C/p>\n\u003Ch3 id=\"bom-and-sourcing-control-set-the-first-quality-boundary\" data-anchor-en=\"bom-and-sourcing-control-set-the-first-quality-boundary\">BOM and sourcing control set the first quality boundary\u003C/h3>\n\u003Cp>The BOM is not only a purchasing list. It is also part of the traceability and release posture for the build.\u003C/p>\n\u003Cp>Questions that belong here include:\u003C/p>\n\u003Cul>\n\u003Cli>whether approved parts and alternates are explicit\u003C/li>\n\u003Cli>whether lifecycle or authenticity concerns are already known\u003C/li>\n\u003Cli>whether polarity, value, package, and sourcing assumptions are stable\u003C/li>\n\u003Cli>whether the build is turnkey, consigned, or mixed\u003C/li>\n\u003C/ul>\n\u003Cp>When those items drift, test results become harder to interpret because the board may no longer match the intended input set.\u003C/p>\n\u003Cp>Related reading:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/turnkey-assembly\">Turnkey Assembly\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/components-bom\">Components BOM\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/component-sourcing\">Component Sourcing\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/assembly-bom-best-practices\">Assembly BOM Best Practices\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ch3 id=\"assembly-definition-controls-whether-the-line-is-testing-the-right-build\" data-anchor-en=\"assembly-definition-controls-whether-the-line-is-testing-the-right-build\">Assembly definition controls whether the line is testing the right build\u003C/h3>\n\u003Cp>An incomplete assembly package creates avoidable ambiguity around:\u003C/p>\n\u003Cul>\n\u003Cli>reference designators and placement notes\u003C/li>\n\u003Cli>polarity and orientation\u003C/li>\n\u003Cli>mixed SMT and THT routing\u003C/li>\n\u003Cli>special handling or selective-process branches\u003C/li>\n\u003Cli>whether the board is still in NPI, pilot, or a more stable repeat build\u003C/li>\n\u003C/ul>\n\u003Cp>That is why assembly quality should never be framed as only a downstream test question.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Input area\u003C/th>\n\u003Cth>Why it matters early\u003C/th>\n\u003Cth>What goes wrong when it stays vague\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>BOM structure\u003C/td>\n\u003Ctd>Keeps the component set stable and traceable\u003C/td>\n\u003Ctd>Wrong value, wrong package, or unclear alternate usage can surface late\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Assembly drawing\u003C/td>\n\u003Ctd>Aligns human and machine interpretation of the build\u003C/td>\n\u003Ctd>Placement, polarity, and process intent drift\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Mixed-process planning\u003C/td>\n\u003Ctd>Separates SMT, THT, selective, and hand-assembly burdens\u003C/td>\n\u003Ctd>The board enters inspection without a clean process path\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>DFM / DFA posture\u003C/td>\n\u003Ctd>Confirms manufacturability and assembly readiness before release\u003C/td>\n\u003Ctd>Later test stages spend time diagnosing preventable build issues\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>For package-cleanup topics, see:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/blog/assembly-drawing-essentials\">Assembly Drawing Essentials\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/mixed-assembly-planning\">Mixed Assembly Planning\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/design-for-assembly-checklist\">Design for Assembly Checklist\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Cp>The governing rule is simple:\u003C/p>\n\u003Cp>\u003Cstrong>when the assembly package is unstable, later test layers become slower and less decisive.\u003C/strong>\u003C/p>\n\u003Ca id=\"method-boundaries\">\u003C/a>\n\u003Ch2 id=\"how-inspection-and-electrical-methods-divide-responsibility\" data-anchor-en=\"how-inspection-and-electrical-methods-divide-responsibility\">How inspection and electrical methods divide responsibility\u003C/h2>\n\u003Cp>The inspection and test stack works best when each method keeps its own boundary.\u003C/p>\n\u003Ch3 id=\"inspection-layers-are-not-interchangeable\" data-anchor-en=\"inspection-layers-are-not-interchangeable\">Inspection layers are not interchangeable\u003C/h3>\n\u003Cp>SPI, AOI, and X-ray do not answer the same question.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Method\u003C/th>\n\u003Cth>What it mainly answers\u003C/th>\n\u003Cth>What it does not prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>SPI\u003C/td>\n\u003Ctd>Whether solder paste deposition is in control before placement and reflow\u003C/td>\n\u003Ctd>Visible assembly correctness after reflow or board electrical behavior\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>AOI\u003C/td>\n\u003Ctd>Whether visible geometry, polarity, placement, and solder features look acceptable\u003C/td>\n\u003Ctd>Hidden-joint integrity or powered functionality\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Whether hidden solder joints and concealed defect areas need inspection evidence\u003C/td>\n\u003Ctd>That visible inspection or functional validation can be skipped\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>That distinction matters because a board can pass optical review and still fail later electrical verification. It can also look electrically stable at one layer while still needing hidden-joint review in dense-package areas.\u003C/p>\n\u003Cp>For more focused inspection topics, see:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/aoi-inspection-pcba\">AOI Inspection for PCBA\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/aoi-spi-best-practices\">AOI and SPI Best Practices\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/spi-vs-aoi-when-to-run-each-in-pcba\">SPI vs AOI in PCBA\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/xray-inspection\">X-Ray Inspection\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ch3 id=\"ict-and-flying-probe-solve-different-electrical-test-problems\" data-anchor-en=\"ict-and-flying-probe-solve-different-electrical-test-problems\">ICT and flying probe solve different electrical-test problems\u003C/h3>\n\u003Cp>The internal quality stack separates fixture-based ICT from fixture-free flying probe.\u003C/p>\n\u003Cp>That boundary is operationally useful:\u003C/p>\n\u003Cul>\n\u003Cli>ICT fits programs that can justify fixture-backed node access and repeatable electrical screening\u003C/li>\n\u003Cli>flying probe fits changing, low-volume, or launch-stage builds where fixture commitment is less attractive\u003C/li>\n\u003C/ul>\n\u003Cp>Neither one should be described as a universal replacement for the other.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Electrical method\u003C/th>\n\u003Cth>Best public framing\u003C/th>\n\u003Cth>What it does not imply\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>ICT\u003C/td>\n\u003Ctd>Fixture-based electrical verification for assembled boards with suitable access and test planning\u003C/td>\n\u003Ctd>That every design has the needed access or should use the same fixture model\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Flying probe\u003C/td>\n\u003Ctd>Fixture-free electrical verification for prototypes, small batches, or changing builds\u003C/td>\n\u003Ctd>That it is simply the same thing as ICT under a different name\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Related reading:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/ict-test\">ICT Test\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/flying-probe-testing\">Flying Probe Testing\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/ict-vs-flying-probe\">ICT vs Flying Probe\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/continuity-test-checklist\">Continuity Test Checklist\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Ch3 id=\"functional-test-belongs-after-the-defect-screening-conversation\" data-anchor-en=\"functional-test-belongs-after-the-defect-screening-conversation\">Functional test belongs after the defect-screening conversation\u003C/h3>\n\u003Cp>FCT answers a different question from ICT or flying probe.\u003C/p>\n\u003Cp>ICT and flying probe are primarily about electrical connectivity and manufacturing-defect screening. FCT is about whether the assembled board behaves correctly in its intended powered context.\u003C/p>\n\u003Cp>That means:\u003C/p>\n\u003Cul>\n\u003Cli>a board can pass AOI and still fail ICT\u003C/li>\n\u003Cli>a board can pass ICT and still fail FCT\u003C/li>\n\u003Cli>a board can pass electrical screening and still need final release review\u003C/li>\n\u003C/ul>\n\u003Cp>The safer explanation is:\u003C/p>\n\u003Cp>\u003Cstrong>inspection, electrical test, and powered behavior validation are related layers, not one interchangeable test bucket.\u003C/strong>\u003C/p>\n\u003Ca id=\"release-gates\">\u003C/a>\n\u003Ch2 id=\"why-release-gates-and-traceability-stay-separate-from-defect-detection\" data-anchor-en=\"why-release-gates-and-traceability-stay-separate-from-defect-detection\">Why release gates and traceability stay separate from defect detection\u003C/h2>\n\u003Cp>Release confidence accumulates across several gates.\u003C/p>\n\u003Cp>Incoming quality control, first-article inspection, final inspection, cleanliness review, and traceability should be treated as governance layers around the build, not as synonyms for AOI or ICT.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Release gate\u003C/th>\n\u003Cth>What it answers\u003C/th>\n\u003Cth>What it does not prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Incoming quality control\u003C/td>\n\u003Ctd>Whether materials and incoming parts are accepted into the build flow\u003C/td>\n\u003Ctd>That the assembled board will perform correctly after assembly\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>First-article inspection\u003C/td>\n\u003Ctd>Whether the first build confirms setup and launch assumptions\u003C/td>\n\u003Ctd>That later production drift cannot happen\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Final inspection\u003C/td>\n\u003Ctd>Whether end-of-line acceptance checks are complete before shipment\u003C/td>\n\u003Ctd>That every upstream process issue was impossible\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Cleanliness review\u003C/td>\n\u003Ctd>Whether contamination-related concerns are being checked where relevant\u003C/td>\n\u003Ctd>That every reliability question is closed for every program\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Traceability\u003C/td>\n\u003Ctd>Whether the build history, component context, and release evidence are recoverable\u003C/td>\n\u003Ctd>That documentation alone guarantees product quality\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>This boundary matters because traceability is evidence, not a defect-detection method by itself.\u003C/p>\n\u003Cp>The same applies to FAI and FQI:\u003C/p>\n\u003Cul>\n\u003Cli>FAI does not replace upstream inspection and test\u003C/li>\n\u003Cli>final inspection does not replace electrical verification\u003C/li>\n\u003Cli>build history does not replace a real release decision\u003C/li>\n\u003C/ul>\n\u003Cp>For gate-specific topics, see:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/incoming-quality-control\">Incoming Quality Control\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/first-article-inspection\">First Article Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/final-quality-inspection\">Final Quality Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/blog/cleanliness-testing-pcb\">Cleanliness Testing for PCB\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Cp>The governing rule is:\u003C/p>\n\u003Cp>\u003Cstrong>release gates decide whether the evidence is complete enough to ship; they do not erase the need for the underlying evidence itself.\u003C/strong>\u003C/p>\n\u003Ca id=\"project-types\">\u003C/a>\n\u003Ch2 id=\"which-project-types-change-the-review-order\" data-anchor-en=\"which-project-types-change-the-review-order\">Which project types change the review order?\u003C/h2>\n\u003Cp>Different build conditions move different quality layers to the top of the review.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Project type\u003C/th>\n\u003Cth>What moves to the top of the review\u003C/th>\n\u003Cth>Deep-dive page\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Prototype or changing NPI build\u003C/td>\n\u003Ctd>fixture-free electrical verification, assembly-definition stability, first-build learning\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/ict-vs-flying-probe\">/en/blog/ict-vs-flying-probe\u003C/a>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Dense package or hidden-joint assembly\u003C/td>\n\u003Ctd>X-ray need, optical boundary limits, hidden-joint evidence\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/xray-inspection\">/en/blog/xray-inspection\u003C/a>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Paste or optical-defect-sensitive SMT build\u003C/td>\n\u003Ctd>SPI and AOI role separation, visible-defect screening order\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/spi-vs-aoi-when-to-run-each-in-pcba\">/en/blog/spi-vs-aoi-when-to-run-each-in-pcba\u003C/a>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Mixed SMT and THT assembly\u003C/td>\n\u003Ctd>process-branch clarity, assembly package definition, inspection routing\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/mixed-assembly-planning\">/en/blog/mixed-assembly-planning\u003C/a>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Documentation-heavy release\u003C/td>\n\u003Ctd>BOM control, assembly drawing completeness, FAI and final release governance\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/assembly-bom-best-practices\">/en/blog/assembly-bom-best-practices\u003C/a>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Assembly-readiness cleanup\u003C/td>\n\u003Ctd>manufacturability, component placement, and DFA alignment before test execution\u003C/td>\n\u003Ctd>\u003Ca href=\"/en/blog/design-for-assembly-checklist\">/en/blog/design-for-assembly-checklist\u003C/a>\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>That table helps separate a quality discussion by build type instead of by generic test buzzwords.\u003C/p>\n\u003Ca id=\"freeze-before-release\">\u003C/a>\n\u003Ch2 id=\"what-should-be-frozen-before-rfq-first-build-or-shipment-release\" data-anchor-en=\"what-should-be-frozen-before-rfq-first-build-or-shipment-release\">What should be frozen before RFQ, first build, or shipment release?\u003C/h2>\n\u003Cp>Before serious RFQ, first build, or shipment release, freeze the items that change the quality path:\u003C/p>\n\u003Col>\n\u003Cli>the BOM structure, sourcing posture, and approved alternates\u003C/li>\n\u003Cli>the assembly package, including drawings, polarity notes, and mixed-process assumptions\u003C/li>\n\u003Cli>the inspection intent, especially where SPI, AOI, or X-ray are expected to answer different defect classes\u003C/li>\n\u003Cli>the electrical-test posture, including whether the build should rely on ICT, flying probe, functional test, or a scoped combination\u003C/li>\n\u003Cli>the release-gate package, including IQC, FAI, final inspection, cleanliness, and traceability expectations\u003C/li>\n\u003Cli>the evidence boundary between manufacturing release, customer acceptance, and any later system-level qualification\u003C/li>\n\u003C/ol>\n\u003Cp>If those items are still moving, the board can still be built, but the quality path is not yet fully defined.\u003C/p>\n\u003Ca id=\"next-steps\">\u003C/a>\n\u003Ch2 id=\"next-steps-with-aptpcb\" data-anchor-en=\"next-steps-with-aptpcb\">Next steps with APTPCB\u003C/h2>\n\u003Cp>If your program is being slowed by an unstable BOM, unclear assembly drawings, uncertain SPI or AOI coverage, hidden-joint inspection questions, ICT versus flying-probe tradeoffs, or missing release-gate evidence, send the Gerbers, BOM, assembly package, and test expectations to \u003Ca href=\"mailto:sales@aptpcb.com\">sales@aptpcb.com\u003C/a> or upload the files through the \u003Ca href=\"/en/quote\">quote page\u003C/a>. APTPCB's team can review the build path and point out whether the main risk sits in input control, inspection planning, electrical verification, or shipment-release governance.\u003C/p>\n\u003Cp>If you need to go deeper before release, review:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/turnkey-assembly\">Turnkey Assembly\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/flying-probe-testing\">Flying Probe Testing\u003C/a>\u003C/li>\n\u003Cli>\u003Ca href=\"/en/pcba/quality-system\">Quality System\u003C/a>\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ca id=\"faq\">\u003C/a>\n\u003Ch2 id=\"faq\" data-anchor-en=\"faq\">FAQ\u003C/h2>\n\u003C!-- faq:start -->\n\n\u003Ch3 id=\"is-aoi-enough-to-say-a-pcba-is-fully-tested\" data-anchor-en=\"is-aoi-enough-to-say-a-pcba-is-fully-tested\">Is AOI enough to say a PCBA is fully tested?\u003C/h3>\n\u003Cp>No. AOI is an optical inspection layer. It does not replace hidden-joint review, electrical verification, functional test, or final release governance.\u003C/p>\n\u003Ch3 id=\"should-every-pcba-use-ict-and-fct\" data-anchor-en=\"should-every-pcba-use-ict-and-fct\">Should every PCBA use ICT and FCT?\u003C/h3>\n\u003Cp>No. The right stack depends on the build stage, design stability, access model, and release intent. Different programs need different combinations of inspection and test layers.\u003C/p>\n\u003Ch3 id=\"is-flying-probe-just-a-lower-cost-version-of-ict\" data-anchor-en=\"is-flying-probe-just-a-lower-cost-version-of-ict\">Is flying probe just a lower-cost version of ICT?\u003C/h3>\n\u003Cp>No. Flying probe and ICT use different access and setup models. They may solve overlapping electrical-screening problems, but they are not the same method.\u003C/p>\n\u003Ch3 id=\"does-first-article-inspection-replace-final-inspection\" data-anchor-en=\"does-first-article-inspection-replace-final-inspection\">Does first-article inspection replace final inspection?\u003C/h3>\n\u003Cp>No. FAI confirms early build and setup assumptions. Final inspection is a separate shipment-release gate later in the flow.\u003C/p>\n\u003Ch3 id=\"does-traceability-prove-reliability-by-itself\" data-anchor-en=\"does-traceability-prove-reliability-by-itself\">Does traceability prove reliability by itself?\u003C/h3>\n\u003Cp>No. Traceability records build history and release evidence. It does not replace defect detection, functional validation, or any separate reliability evaluation.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Ca id=\"references\">\u003C/a>\n\u003Ch2 id=\"public-references\" data-anchor-en=\"public-references\">Public references\u003C/h2>\n\u003Col>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/testing-quality\">APTPCB Testing & Quality\u003C/a>\u003Cbr>Supports the layered PCBA quality flow across inspection, electrical test, and release governance.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/aoi-inspection\">APTPCB AOI Inspection\u003C/a>\u003Cbr>Supports AOI as a visible-defect inspection layer rather than a universal test claim.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/xray-inspection\">APTPCB X-Ray Inspection\u003C/a>\u003Cbr>Supports hidden-joint and concealed-defect inspection boundaries.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/ict-test\">APTPCB ICT Test\u003C/a>\u003Cbr>Supports fixture-based electrical verification for assembled boards.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/flying-probe-testing\">APTPCB Flying Probe Testing\u003C/a>\u003Cbr>Supports fixture-free electrical verification for changing or lower-volume builds.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"/en/pcba/first-article-inspection\">APTPCB First Article Inspection\u003C/a>\u003Cbr>Supports first-build confirmation as a separate release gate.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://kohyoung.com/en/solder-paste-inspection-technology\">Koh Young: Solder Paste Inspection Technology\u003C/a>\u003Cbr>Supports SPI as an upstream paste-measurement and print-process control layer.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://kohyoung.com/en/automated-optical-inspection-technology\">Koh Young: Automated Optical Inspection Technology\u003C/a>\u003Cbr>Supports AOI as an optical method for assembled geometry and solder features.\u003C/p>\n\u003C/li>\n\u003Cli>\u003Cp>\u003Ca href=\"https://www.keysight.com/us/en/products/in-circuit-test-for-manufacturing/in-circuit-test-systems.html\">Keysight: In-Circuit Test Systems\u003C/a>\u003Cbr>Supports ICT as a production-line electrical fault-screening method.\u003C/p>\n\u003C/li>\n\u003C/ol>\n\u003Ca id=\"author\">\u003C/a>\n\u003Ch2 id=\"author-and-review-information\" data-anchor-en=\"author-and-review-information\">Author and review information\u003C/h2>\n\u003Cul>\n\u003Cli>Author: APTPCB PCB and PCBA process content team\u003C/li>\n\u003Cli>Technical review: PCBA assembly, inspection, electrical-test, and release-governance engineering team\u003C/li>\n\u003Cli>Last updated: 2026-05-13\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/pcba/testing-quality\">Testing & Quality\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/turnkey-assembly\">Turnkey Assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/aoi-inspection\">AOI Inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/components-bom\">Components BOM\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/component-sourcing\">Component Sourcing\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/assembly-bom-best-practices\">Assembly BOM Best Practices\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/assembly-drawing-essentials\">Assembly Drawing Essentials\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,15,16,17,18],"pcba assembly","pcb testing","pcba quality","ict test","flying probe testing","pcba-assembly-test-quality-guide",{"blog":21,"breadcrumb":30,"faq":44},{"@context":22,"@type":23,"headline":4,"description":5,"image":8,"url":24,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":25,"articleSection":7,"author":26,"publisher":29},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/pcba-assembly-test-quality-guide","pcba assembly, pcb testing, pcba quality, ict test, flying probe testing",{"@type":27,"name":28},"Organization","APTPCB",{"@type":27,"name":28},{"@context":22,"@type":31,"itemListElement":32},"BreadcrumbList",[33,38,42],{"@type":34,"position":35,"name":36,"item":37},"ListItem",1,"Home","https://aptpcb.com/",{"@type":34,"position":39,"name":40,"item":41},2,"Blog","https://aptpcb.com/en/blog",{"@type":34,"position":43,"name":19,"item":24},3,{"@context":22,"@type":45,"mainEntity":46},"FAQPage",[47,53,57,61,65],{"@type":48,"name":49,"acceptedAnswer":50},"Question","Is AOI enough to say a PCBA is fully tested?",{"@type":51,"text":52},"Answer","No. AOI is an optical inspection layer. It does not replace hidden-joint review, electrical verification, functional test, or final release governance.",{"@type":48,"name":54,"acceptedAnswer":55},"Should every PCBA use ICT and FCT?",{"@type":51,"text":56},"No. The right stack depends on the build stage, design stability, access model, and release intent. Different programs need different combinations of inspection and test layers.",{"@type":48,"name":58,"acceptedAnswer":59},"Is flying probe just a lower-cost version of ICT?",{"@type":51,"text":60},"No. Flying probe and ICT use different access and setup models. They may solve overlapping electrical-screening problems, but they are not the same method.",{"@type":48,"name":62,"acceptedAnswer":63},"Does first-article inspection replace final inspection?",{"@type":51,"text":64},"No. FAI confirms early build and setup assumptions. Final inspection is a separate shipment-release gate later in the flow.",{"@type":48,"name":66,"acceptedAnswer":67},"Does traceability prove reliability by itself?",{"@type":51,"text":68},"No. Traceability records build history and release evidence. It does not replace defect detection, functional validation, or any separate reliability evaluation.",{"pcbManufacturingColumns":70,"capabilityColumns":195,"resourceColumns":226,"pcbaColumns":266},[71,119,148,177],{"heading":72,"links":73},"PCB Product Families",[74,77,80,83,86,89,92,95,98,101,104,107,110,113,116],{"label":75,"path":76},"FR-4 PCB","/pcb/fr4-pcb",{"label":78,"path":79},"High-Speed PCB","/pcb/high-speed-pcb",{"label":81,"path":82},"Multilayer PCB","/pcb/multilayer-pcb",{"label":84,"path":85},"HDI PCB","/pcb/hdi-pcb",{"label":87,"path":88},"Flexible PCB","/pcb/flex-pcb",{"label":90,"path":91},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":93,"path":94},"Ceramic PCB","/pcb/ceramic-pcb",{"label":96,"path":97},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":99,"path":100},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":102,"path":103},"Antenna PCB","/pcb/antenna-pcb",{"label":105,"path":106},"High Frequency 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