[{"data":1,"prerenderedAt":404},["ShallowReactive",2],{"blog-solderability-testing-en":3,"header-nav-en":68},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":38,"slug":42,"jsonld":43},"PCB Solderability Testing: Choosing the Right Evidence for Pads, Holes and Component Terminations","Solderability testing evaluates a defined surface under agreed conditions. Match the specimen, test method, evidence and acceptance criteria to the decision.","2026-11-05","assembly","/assets/img/blogs/2026/11/solderability-evidence-concept.svg",12,2341,"PT12M","\u003Cp>Solderability testing asks whether a \u003Cstrong>defined surface can be wetted by solder under specified conditions\u003C/strong>. The surface might be a PCB pad, plating inside a hole, or a component termination. A useful result identifies that specimen, the test conditions and the agreed acceptance criteria—not just a “pass” label.\u003C/p>\n\u003Cp>For procurement and engineering teams, the first decision is what needs to be evaluated. A component solderability report is evidence about the tested component terminations; it is not a test of the PCB pads they will be soldered to. Likewise, an edge-dip result for a board sample does not necessarily describe solderability inside plated holes.\u003C/p>\n\u003Cp>A passing test can support a release decision within its stated scope. It does not, by itself, demonstrate the quality of every assembled joint or establish long-term product reliability.\u003C/p>\n\u003Cfigure>\n  \u003Cimg src=\"/assets/img/blogs/2026/11/solderability-evidence-concept.svg\" alt=\"Conceptual worksheet for comparing solderability test specimen, conditions, result and acceptance evidence\">\n  \u003Cfigcaption>Conceptual evidence worksheet, not a test report or measured wetting curve. Comparable decisions require the specimen and conditions as well as the result.\u003C/figcaption>\n\u003C/figure>\n\n\u003Ch2 id=\"start-with-the-surface-and-the-decision\" data-anchor-en=\"start-with-the-surface-and-the-decision\">Start with the surface and the decision\u003C/h2>\n\u003Cp>Before selecting a method, describe the surface of concern and the decision the result must support:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Bare-board surface:\u003C/strong> Identify the pad, exposed finish or other board feature, the fabrication lot and its storage history.\u003C/li>\n\u003Cli>\u003Cstrong>Plated hole:\u003C/strong> Identify the hole or hole population and whether the question concerns its internal plating. A test of an exposed board edge is not automatically evidence for the hole wall.\u003C/li>\n\u003Cli>\u003Cstrong>Component termination:\u003C/strong> Identify the component part, package or lead style, manufacturer lot, and prior handling or conditioning.\u003C/li>\n\u003Cli>\u003Cstrong>Assembly process:\u003C/strong> Identify the board, components, materials and process to be represented. A process trial evaluates their interaction, rather than isolating a single surface.\u003C/li>\n\u003C/ul>\n\u003Cp>The distinction matters because the surface finish, exposed geometry and prior history can change the outcome. A result for one component package, board feature or lot should not be assumed to apply to another without an agreed basis.\u003C/p>\n\u003Cp>IPC’s \u003Cem>J-STD-002, Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires\u003C/em>, addresses component-related specimens. IPC’s \u003Cem>J-STD-003, Solderability Tests for Printed Boards\u003C/em>, addresses printed boards. Specify the applicable document, revision and method in the purchase or quality agreement; do not rely on a standard number alone to settle every sampling or release question.\u003C/p>\n\u003Ch2 id=\"choose-the-method-for-the-question\" data-anchor-en=\"choose-the-method-for-the-question\">Choose the method for the question\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Approach\u003C/th>\n\u003Cth>What the result describes\u003C/th>\n\u003Cth>Useful when\u003C/th>\n\u003Cth>Conditions and limits\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Visual dip-and-look\u003C/strong>\u003C/td>\n\u003Ctd>The appearance of the defined surface after the prescribed preparation, fluxing and solder exposure\u003C/td>\n\u003Ctd>A defined board feature or termination needs to be assessed against visual acceptance criteria\u003C/td>\n\u003Ctd>The agreed method must specify what area to examine and how to judge it, including any relevant coverage and defect criteria. Appearance is an evaluated result, not an absence of criteria.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Wetting balance\u003C/strong>\u003C/td>\n\u003Ctd>A force-versus-time response as the defined specimen interacts with molten solder\u003C/td>\n\u003Ctd>A measured wetting response is needed under controlled conditions\u003C/td>\n\u003Ctd>Geometry, solder, flux, immersion setup and timing affect the curve. A curve is not automatically a pass or fail; acceptance limits must be agreed.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Process simulation or assembly trial\u003C/strong>\u003C/td>\n\u003Ctd>The observed outcome when selected boards, components and materials undergo a defined process\u003C/td>\n\u003Ctd>The concern is how the chosen surfaces behave together in a representative assembly process\u003C/td>\n\u003Ctd>It can expose interactions that a separate specimen test misses, but the outcome may not isolate the cause. Inspection and acceptance criteria must still be defined.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>These approaches answer related but different questions. Use one or more according to the decision, not simply because a report happens to be available.\u003C/p>\n\u003Ch3 id=\"visual-dip-and-look-specify-what-acceptable-means\" data-anchor-en=\"visual-dip-and-look-specify-what-acceptable-means\">Visual dip-and-look: specify what “acceptable” means\u003C/h3>\n\u003Cp>In a visual test, the specimen is exposed to solder under the selected procedure and then examined against the applicable criteria. The report should distinguish \u003Cstrong>what was observed\u003C/strong> from \u003Cstrong>whether the observation met the agreed requirement\u003C/strong>.\u003C/p>\n\u003Cp>For example, a report may describe the relevant surface area and observed solder coverage or defects, then record the disposition against the specified method. The applicable criteria depend on the specimen and agreement; there is no useful universal coverage value to substitute for them.\u003C/p>\n\u003Cp>Visual assessment also has limits. An image of an untreated pad or termination can help identify contamination, damage or finish appearance, but it cannot by itself guarantee that the surface will wet. A post-test photograph can document what was seen, but its value depends on identifying the specimen, viewed area and criteria used.\u003C/p>\n\u003Ch3 id=\"wetting-balance-measured-does-not-mean-self-accepting\" data-anchor-en=\"wetting-balance-measured-does-not-mean-self-accepting\">Wetting balance: measured does not mean self-accepting\u003C/h3>\n\u003Cp>A wetting balance records a force response over time as a specimen contacts molten solder. The curve can help describe the development of wetting under the test conditions. Depending on the procedure and agreement, the report may include the curve and defined values derived from it.\u003C/p>\n\u003Cp>Those measurements need context. A small termination and a broad PCB feature do not present the same geometry. Different fluxes, alloys, specimen preparation, immersion arrangements or timing can also change the response. Instrument setup, any corrections required by the method, and the reported reference points matter when comparing curves.\u003C/p>\n\u003Cp>The National Physical Laboratory’s \u003Cem>Measurement Good Practice Guide 66, Issue 2\u003C/em> discusses solderability measurement and wetting force over time. Its examples and conditions are useful for understanding the technique; they are not automatic acceptance limits for every specimen. Agree on the method and limits before testing, including what will happen if the result falls outside them.\u003C/p>\n\u003Ch3 id=\"process-simulation-test-the-interaction-you-care-about\" data-anchor-en=\"process-simulation-test-the-interaction-you-care-about\">Process simulation: test the interaction you care about\u003C/h3>\n\u003Cp>An agreed process simulation can be useful when separate board and component evidence does not resolve an assembly concern. For example, a trial might combine representative boards, components, solder material and flux in a defined process, then inspect selected joints against agreed criteria.\u003C/p>\n\u003Cp>The trial should record which materials and process settings were used, how specimens were selected, and what differences remain from the intended production process. If the trial shows poor results, the board finish, component termination, solder material, process or their interaction may all need investigation. Do not assign the cause from the trial outcome alone.\u003C/p>\n\u003Cp>An assembly trial is also not a substitute for defining the bare-board or component test when either is contractually required. Solder paste inspection and automated optical inspection address different stages of assembly; see \u003Ca href=\"/en/blog/spi-vs-aoi-when-to-run-each-in-pcba\">when to run SPI and AOI in PCBA\u003C/a>.\u003C/p>\n\u003Ch2 id=\"internal-holes-need-their-own-test-question\" data-anchor-en=\"internal-holes-need-their-own-test-question\">Internal holes need their own test question\u003C/h2>\n\u003Cp>A plated through-hole creates a specific evidence challenge: the surface of interest may be inside the board rather than on an exposed pad or edge. State whether the concern is the pad, the hole wall, or both, and select a specimen and method that address that location.\u003C/p>\n\u003Cp>IPC’s \u003Cem>TM-650 2.4.12, Revision A, 1991, Solderability, Edge Dip Method\u003C/em> is an older method for an edge-dip evaluation. Its own scope cautions that the result does not necessarily represent the solderability of internal hole plating. It should not be treated as a current universal hole-test procedure or used to infer a hole result from an edge result.\u003C/p>\n\u003Cp>For a through-hole process concern, also consider whether a representative assembly trial is needed to examine the combined effect of the board, termination and process. The practical context is discussed in \u003Ca href=\"/en/blog/through-hole-soldering-basics\">through-hole soldering basics\u003C/a>.\u003C/p>\n\u003Ch2 id=\"what-a-useful-report-should-transfer\" data-anchor-en=\"what-a-useful-report-should-transfer\">What a useful report should transfer\u003C/h2>\n\u003Cp>Ask the test requester, laboratory and release authority to agree on the following before samples are consumed. The final report should retain enough of this information to interpret the result later.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Item\u003C/th>\n\u003Cth>What to record or resolve\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Specimen identity\u003C/strong>\u003C/td>\n\u003Ctd>PCB part and revision, feature or hole location, or component part and termination; finish where known; unique sample identifiers.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Lot and selection\u003C/strong>\u003C/td>\n\u003Ctd>Manufacturing lot, quantity represented, sample-selection approach and any known reason the samples may not represent the lot.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>History\u003C/strong>\u003C/td>\n\u003Ctd>Relevant receipt and storage information, handling, prior processing and conditioning, including any treatment specified before the test.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Method\u003C/strong>\u003C/td>\n\u003Ctd>Document and contracted revision, procedure, specimen orientation and preparation, plus the defined test conditions.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Materials and setup\u003C/strong>\u003C/td>\n\u003Ctd>Solder alloy, flux, equipment setup, timing and other conditions required by the selected method.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Acceptance\u003C/strong>\u003C/td>\n\u003Ctd>Criteria agreed before testing, including the surface or measurement to be judged and who can authorize disposition.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Result\u003C/strong>\u003C/td>\n\u003Ctd>Visual observations and disposition, or measured values and curves as applicable; deviations, inconclusive observations and the report date.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Next action\u003C/strong>\u003C/td>\n\u003Ctd>Release, hold, investigation, additional testing or another approved disposition, with an owner.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>STMicroelectronics’ \u003Cem>AN2036, Solderability Tests\u003C/em> is useful as an example of solderability testing in a particular product context. Its conditions and criteria should not be copied into an unrelated board or component agreement without confirming applicability.\u003C/p>\n\u003Ch3 id=\"the-sample-is-not-the-lot\" data-anchor-en=\"the-sample-is-not-the-lot\">The sample is not the lot\u003C/h3>\n\u003Cp>A report describes the samples actually tested. Whether it supports a decision on a larger lot depends on the agreed sampling plan, how specimens were selected and whether their condition represents the material to be released.\u003C/p>\n\u003Cp>A board coupon, for example, may be convenient to test, but its relevance to a particular pad or hole needs to be established. A component sample from a different manufacturer lot or storage history may not answer the present question. Preserve the connection between samples, packaging and the represented inventory; \u003Ca href=\"/en/blog/pcb-traceability-lot-control\">PCB traceability and lot control\u003C/a> provides related guidance.\u003C/p>\n\u003Cp>Solder exposure and preparation can alter or consume a specimen. Keep tested items segregated and do not return them to assembly as normal stock unless an authorized disposition permits it. If the only available item is an intact production board, agree in advance whether testing would damage or contaminate features needed for assembly. Reserve representative samples where possible.\u003C/p>\n\u003Cfigure>\n  \u003Cimg src=\"/assets/img/blogs/2026/11/pcb-copper-traces-reference.jpg\" alt=\"Close view of an ordinary circuit board with soldered joints and visible board features\">\n  \u003Cfigcaption>Ordinary soldered joints on a circuit board. Photo: Tima Miroshnichenko / Pexels. This is not a solderability test, test sample, report, APTPCB work or acceptance result.\u003C/figcaption>\n\u003C/figure>\n\n\u003Ch2 id=\"hypothetical-conflict-a-component-report-arrives-but-the-concern-is-a-pcb-pad\" data-anchor-en=\"hypothetical-conflict-a-component-report-arrives-but-the-concern-is-a-pcb-pad\">Hypothetical conflict: a component report arrives, but the concern is a PCB pad\u003C/h2>\n\u003Cp>\u003Cstrong>Invented example:\u003C/strong> A buyer receives a component solderability report marked “pass.” The assembly engineer is concerned about wetting on a PCB pad from the boards awaiting assembly. No actual pad test result is available in this example.\u003C/p>\n\u003Cp>The report is not contradictory, and it does not establish that either item failed. It addresses a different specimen: the component termination rather than the board pad.\u003C/p>\n\u003Cp>The team should first request or confirm:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Report and sample identity:\u003C/strong> Which component part, termination and samples were tested? What PCB part, revision and pad are in question?\u003C/li>\n\u003Cli>\u003Cstrong>Date and lot:\u003C/strong> When was the component tested, and does its lot match the material to be assembled? Which board lot is affected?\u003C/li>\n\u003Cli>\u003Cstrong>Prior conditioning and history:\u003C/strong> How were the tested components and the boards stored, handled or otherwise conditioned?\u003C/li>\n\u003Cli>\u003Cstrong>Method and acceptance:\u003C/strong> What procedure, conditions and criteria produced the component disposition? What method and criteria would address the pad?\u003C/li>\n\u003Cli>\u003Cstrong>Next action and authority:\u003C/strong> Who decides whether to hold the board lot, request representative pad testing, run a process trial or proceed under an approved disposition?\u003C/li>\n\u003C/ol>\n\u003Cp>If the component report lacks key identifiers or conditions, request clarification rather than treating its pass label as complete evidence. If a pad test is commissioned, define its specimen and acceptance before testing. If both separate tests pass but a representative assembly trial has an unfavorable result, investigate the combined materials and process rather than declaring either report invalid.\u003C/p>\n\u003Ch2 id=\"handle-exceptions-without-turning-a-retest-into-rework\" data-anchor-en=\"handle-exceptions-without-turning-a-retest-into-rework\">Handle exceptions without turning a retest into rework\u003C/h2>\n\u003Cp>An inconclusive observation, a missing condition or a result outside the agreed criteria calls for a documented decision—not an automatic repeat until a favorable result appears.\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Hold the affected material as appropriate.\u003C/strong> Identify the potentially affected lot and prevent unapproved release while the discrepancy is assessed.\u003C/li>\n\u003Cli>\u003Cstrong>Check validity first.\u003C/strong> Confirm specimen identity, method, equipment status, setup, conditioning, observations and any deviations. A documented test error may justify an agreed repeat.\u003C/li>\n\u003Cli>\u003Cstrong>Keep retesting distinct from rework.\u003C/strong> Retesting may assess additional, previously untested or, where the method permits, previously tested samples under an agreed plan; the sample history must be recorded. Rework or surface treatment changes the material; testing after that change evaluates the treated condition, not necessarily the original lot condition.\u003C/li>\n\u003Cli>\u003Cstrong>Agree on representation again.\u003C/strong> If material is treated, define which items received the treatment, how they will be identified and what samples represent them. Do not extend a result to untreated or differently handled stock without justification.\u003C/li>\n\u003Cli>\u003Cstrong>Record the disposition.\u003C/strong> The designated release authority should approve the evidence and next action under the contract or quality system.\u003C/li>\n\u003C/ul>\n\u003Cp>Cleaning can be relevant to an assembly investigation, but it is not a substitute for an agreed solderability test or an authorized recovery process. For the separate issue of assembly residues, see \u003Ca href=\"/en/blog/cleaning-after-soldering\">cleaning after soldering\u003C/a>.\u003C/p>\n\u003Ch2 id=\"a-practical-handoff-to-aptpcb\" data-anchor-en=\"a-practical-handoff-to-aptpcb\">A practical handoff to APTPCB\u003C/h2>\n\u003Cp>For a project discussion, include the board or component identity, affected lot, feature of concern, available reports, intended assembly process and the standard revision and acceptance requirements you want applied. Identify any missing information as unresolved rather than assuming a default method.\u003C/p>\n\u003Cp>Use \u003Ca href=\"/en/quote\">request a quote\u003C/a> for a project inquiry or \u003Ca href=\"/en/contact\">contact APTPCB\u003C/a> to discuss the required documentation and next steps. Confirm the testing arrangements and responsibilities explicitly; do not assume a particular test or report is included.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"public-reference-documents\" data-anchor-en=\"public-reference-documents\">Public reference documents\u003C/h2>\n\u003Cul>\n\u003Cli>IPC, \u003Cem>J-STD-002, Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires\u003C/em> — component-related scope; use the revision agreed in the contract.\u003C/li>\n\u003Cli>IPC, \u003Cem>J-STD-003, Solderability Tests for Printed Boards\u003C/em> — printed-board scope; use the revision agreed in the contract.\u003C/li>\n\u003Cli>IPC, \u003Cem>TM-650 2.4.12, Revision A, 1991, Solderability, Edge Dip Method\u003C/em> — older edge-dip method; not necessarily representative of internal hole plating.\u003C/li>\n\u003Cli>National Physical Laboratory, \u003Cem>Measurement Good Practice Guide 66, Issue 2\u003C/em> — wetting-force measurement context; its examples are not universal acceptance criteria.\u003C/li>\n\u003Cli>STMicroelectronics, \u003Cem>AN2036, Solderability Tests\u003C/em> — product-specific test context; its conditions should not be generalized without checking applicability.\u003C/li>\n\u003C/ul>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/spi-vs-aoi-when-to-run-each-in-pcba\">when to run SPI and AOI in PCBA\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/through-hole-soldering-basics\">through-hole soldering basics\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-traceability-lot-control\">PCB traceability and lot control\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/cleaning-after-soldering\">cleaning after soldering\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">request a quote\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact APTPCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32,35],{"id":15,"text":16},"start-with-the-surface-and-the-decision","Start with the surface and the decision",{"id":18,"text":19},"choose-the-method-for-the-question","Choose the method for the question",{"id":21,"text":22},"internal-holes-need-their-own-test-question","Internal holes need their own test question",{"id":24,"text":25},"what-a-useful-report-should-transfer","What a useful report should transfer",{"id":27,"text":28},"hypothetical-conflict-a-component-report-arrives-but-the-concern-is-a-pcb-pad","Hypothetical conflict: a component report arrives, but the concern is a PCB pad",{"id":30,"text":31},"handle-exceptions-without-turning-a-retest-into-rework","Handle exceptions without turning a retest into rework",{"id":33,"text":34},"a-practical-handoff-to-aptpcb","A practical handoff to APTPCB",{"id":36,"text":37},"public-reference-documents","Public reference documents",[39,40,41],"solderability testing","wetting balance","PCB testing","solderability-testing",{"blog":44,"breadcrumb":53,"faq":67},{"@context":45,"@type":46,"headline":4,"description":5,"image":8,"url":47,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":48,"articleSection":7,"author":49,"publisher":52},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/solderability-testing","solderability testing, wetting balance, PCB testing",{"@type":50,"name":51},"Organization","APTPCB",{"@type":50,"name":51},{"@context":45,"@type":54,"itemListElement":55},"BreadcrumbList",[56,61,65],{"@type":57,"position":58,"name":59,"item":60},"ListItem",1,"Home","https://aptpcb.com/",{"@type":57,"position":62,"name":63,"item":64},2,"Blog","https://aptpcb.com/en/blog",{"@type":57,"position":66,"name":42,"item":47},3,null,{"pcbManufacturingColumns":69,"capabilityColumns":197,"resourceColumns":233,"pcbaColumns":277},[70,118,147,176],{"heading":71,"links":72},"PCB Product Families",[73,76,79,82,85,88,91,94,97,100,103,106,109,112,115],{"label":74,"path":75},"FR-4 PCB","/pcb/fr4-pcb",{"label":77,"path":78},"High-Speed PCB","/pcb/high-speed-pcb",{"label":80,"path":81},"Multilayer PCB","/pcb/multilayer-pcb",{"label":83,"path":84},"HDI PCB","/pcb/hdi-pcb",{"label":86,"path":87},"Flexible PCB","/pcb/flex-pcb",{"label":89,"path":90},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":92,"path":93},"Ceramic PCB","/pcb/ceramic-pcb",{"label":95,"path":96},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":98,"path":99},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":101,"path":102},"Antenna PCB","/pcb/antenna-pcb",{"label":104,"path":105},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":107,"path":108},"Microwave PCB","/pcb/microwave-pcb",{"label":110,"path":111},"Metal Core PCB","/pcb/metal-core-pcb",{"label":113,"path":114},"High-Tg PCB","/pcb/high-tg-pcb",{"label":116,"path":117},"Backplane PCB","/pcb/backplane-pcb",{"sections":119},[120],{"heading":121,"links":122},"RF & Materials",[123,126,129,132,135,138,141,144],{"label":124,"path":125},"Rogers PCB","/materials/rf-rogers",{"label":127,"path":128},"Taconic PCB","/materials/taconic-pcb",{"label":130,"path":131},"Teflon PCB","/materials/teflon-pcb",{"label":133,"path":134},"Arlon PCB","/materials/arlon-pcb",{"label":136,"path":137},"Megtron PCB","/materials/megtron-pcb",{"label":139,"path":140},"ISOLA PCB","/materials/isola-pcb",{"label":142,"path":143},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":145,"path":146},"Impedance Control","/pcb/pcb-impedance-control",{"sections":148},[149],{"heading":150,"links":151},"Manufacturing / Stackups",[152,155,158,161,164,167,170,173],{"label":153,"path":154},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":156,"path":157},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":159,"path":160},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":162,"path":163},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":165,"path":166},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":168,"path":169},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":171,"path":172},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":174,"path":175},"Multi-Layer Laminated Structure","/pcb/multilayer-pcb-lamination-services",{"heading":177,"links":178},"Specialties & Resources",[179,182,185,188,191,194],{"label":180,"path":181},"PCB Design & Layout Services","/pcba/pcb-design-services",{"label":183,"path":184},"PCB Surface Finishes","/pcb/pcb-surface-finishes",{"label":186,"path":187},"PCB Drilling & Vias","/pcb/pcb-drilling",{"label":189,"path":190},"PCB Stackup","/pcb/pcb-stack-up",{"label":192,"path":193},"PCB Profiling","/pcb/pcb-profiling",{"label":195,"path":196},"Quality & Inspection","/pcb/pcb-quality",[198,203,208,213,218,223,228],{"links":199},[200],{"label":201,"path":202},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":204},[205],{"label":206,"path":207},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":209},[210],{"label":211,"path":212},"Flex PCB Capability","/capabilities/flex-pcb",{"links":214},[215],{"label":216,"path":217},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":219},[220],{"label":221,"path":222},"Metal PCB Capability","/capabilities/metal-pcb",{"links":224},[225],{"label":226,"path":227},"Ceramic PCB Capability","/capabilities/ceramic-pcb",{"links":229},[230],{"label":231,"path":232},"Heavy Copper PCB Capability","/capabilities/heavy-copper-pcb",[234,245,269],{"heading":235,"links":236},"Downloads",[237,240,243],{"label":238,"path":239},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":241,"path":242},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":174,"path":244},"/pcb/multi-layer-laminated-structure",{"heading":246,"links":247},"Tools",[248,251,254,257,260,263,266],{"label":249,"path":250},"Gerber Viewer","/tools/gerber-viewer",{"label":252,"path":253},"PCB Viewer","/tools/pcb-viewer",{"label":255,"path":256},"BOM Viewer","/tools/bom-viewer",{"label":258,"path":259},"3D Viewer","/tools/3d-viewer",{"label":261,"path":262},"Circuit Simulator","/tools/circuit-simulator",{"label":264,"path":265},"Impedance Calculator","/tools/impedance-calculator",{"label":267,"path":268},"Trace Width Calculator","/tools/trace-width-calculator",{"heading":270,"links":271},"FAQ & Blog",[272,275],{"label":273,"path":274},"FAQ","/resources/faq",{"label":63,"path":276},"/blog",[278,308,334,367],{"heading":279,"links":280},"Core Services",[281,284,287,290,293,296,299,302,305],{"label":282,"path":283},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":285,"path":286},"NPI & Small Batch PCB Assembly","/pcba/npi-assembly",{"label":288,"path":289},"Mass Production PCB Assembly","/pcba/mass-production",{"label":291,"path":292},"Flex & Rigid-Flex PCB Assembly","/pcba/flex-rigid-flex",{"label":294,"path":295},"SMT & Through-Hole Assembly","/pcba/smt-tht",{"label":297,"path":298},"BGA PCB Assembly","/pcba/bga-qfn-fine-pitch",{"label":300,"path":301},"Components & BOM Management","/pcba/components-bom",{"label":303,"path":304},"Box Build Assembly","/pcba/box-build-assembly",{"label":306,"path":307},"PCB Assembly Testing & Quality","/pcba/testing-quality",{"heading":309,"links":310},"Supporting Services",[311,313,316,319,322,325,328,331],{"label":312,"path":181},"PCB Design & Layout",{"label":314,"path":315},"Every Support Touchpoint","/pcba/support-services",{"label":317,"path":318},"Stencil Lab","/pcba/pcb-stencil",{"label":320,"path":321},"Components Sourcing","/pcba/component-sourcing",{"label":323,"path":324},"IC Programming","/pcba/ic-programming",{"label":326,"path":327},"Conformal Coating","/pcba/pcb-conformal-coating",{"label":329,"path":330},"Selective Soldering","/pcba/pcb-selective-soldering",{"label":332,"path":333},"BGA Reballing","/pcba/bga-reballing",{"heading":335,"links":336},"Quality & Testing",[337,340,343,346,349,352,355,358,361,364],{"label":338,"path":339},"Quality Inspection","/pcba/quality-system",{"label":341,"path":342},"First Article Inspection (FAI)","/pcba/first-article-inspection",{"label":344,"path":345},"Solder Paste Inspection (SPI)","/pcba/spi-inspection",{"label":347,"path":348},"AOI Optical Inspection","/pcba/aoi-inspection",{"label":350,"path":351},"X-Ray / CT Inspection","/pcba/xray-inspection",{"label":353,"path":354},"ICT In-Circuit Testing","/pcba/ict-test",{"label":356,"path":357},"Flying Probe Testing","/pcba/flying-probe-testing",{"label":359,"path":360},"FCT / Functional Testing","/pcba/fct-test",{"label":362,"path":363},"Final Inspection & Packing","/pcba/final-quality-inspection",{"label":365,"path":366},"Incoming Quality Control","/pcba/incoming-quality-control",{"heading":368,"linkClass":369,"links":370},"Industry Applications (Entry)","text-nowrap",[371,374,377,380,383,386,389,392,395,398,401],{"label":372,"path":373},"Server / Data Center","/industries/server-data-center-pcb",{"label":375,"path":376},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":378,"path":379},"Medical","/industries/medical-pcb",{"label":381,"path":382},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":384,"path":385},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":387,"path":388},"Drone / UAV","/industries/drone-uav-pcb",{"label":390,"path":391},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":393,"path":394},"Power & New Energy","/industries/power-energy-pcb",{"label":396,"path":397},"Robotics & Automation","/industries/robotics-pcb",{"label":399,"path":400},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":402,"path":403},"PCB Industry Overview →","/pcb-industry-solutions",1793859432813]