[{"data":1,"prerenderedAt":411},["ShallowReactive",2],{"blog-via-tenting-pcb-en":3,"header-nav-en":75},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tableOfContents":13,"tags":44,"slug":49,"jsonld":50},"PCB Via Tenting: When to Cover, Expose, Plug or Fill a Via","Choose PCB via tenting, mask openings, plugging or filling by purpose, and specify the treatment and acceptance for each side.","2026-11-03","manufacturing","/assets/img/blogs/2026/11/via-mask-treatment-concept.png",10,1854,"PT10M","\u003Cp>Via tenting means covering a via with solder mask on one or both sides of a PCB. It can reduce exposed copper around a via, but a mask-covered opening is not proof that the hole is sealed, filled, watertight or suitable as a flat solderable pad. If the design needs one of those outcomes, specify it separately and agree on how it will be verified.\u003C/p>\n\u003Cp>That distinction matters most where vias sit close to component pads, need to remain accessible for testing, or occupy a soldered pad. The right treatment is a location-specific decision, not a single setting for the entire board.\u003C/p>\n\u003Cimg src=\"/assets/img/blogs/2026/11/via-mask-treatment-concept.png\" alt=\"Conceptual top views of an exposed via and a via covered by solder mask\">\n\n\u003Cp>In these conceptual top views, \u003Cstrong>1\u003C/strong> shows an exposed via and \u003Cstrong>2\u003C/strong> shows mask covering the via. They are not to scale; a top view cannot prove that a covered hole is sealed.\u003C/p>\n\u003Ch2 id=\"what-does-a-tented-via-actually-cover\" data-anchor-en=\"what-does-a-tented-via-actually-cover\">What does a tented via actually cover?\u003C/h2>\n\u003Cp>The layout specifies where the solder mask is open and where it remains over copper. A tenting setting requests mask coverage over a via. KiCad 9's PCB Editor documentation, for example, treats front and back tenting as separate controls. The finished result still depends on the exported mask data, hole geometry and the fabrication process.\u003C/p>\n\u003Cp>Mask coverage is different from inserting material into the hole. A designer who needs a plugged hole, a filled barrel or a copper-capped surface should state that requirement rather than expect the fabricator to infer it from a mask layer. The public preview of IPC-4761 lists tented, plugged, filled, covered and capped constructions separately and discusses how protection should be specified in procurement documentation. It does not supply a universal acceptance limit for every project.\u003C/p>\n\u003Ch2 id=\"which-treatment-should-be-specified\" data-anchor-en=\"which-treatment-should-be-specified\">Which treatment should be specified?\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Design need\u003C/th>\n\u003Cth>Treatment to discuss\u003C/th>\n\u003Cth>What needs confirmation\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Reduce exposed copper around a via\u003C/td>\n\u003Ctd>Solder-mask cover on the relevant side\u003C/td>\n\u003Ctd>Locations, side, exported mask and the agreed coverage criteria; do not assume the hole is sealed.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Access for a test probe or other contact\u003C/td>\n\u003Ctd>Mask opening at selected vias\u003C/td>\n\u003Ctd>Accessible side, opening and location; confirm the planned test access with the assembly and test teams.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Control entry into a via\u003C/td>\n\u003Ctd>A separately specified plugging or filling process\u003C/td>\n\u003Ctd>Material and extent, sides, inspection and the result required for the application; a mask cover alone does not establish it.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Solder onto a pad containing a via\u003C/td>\n\u003Ctd>A defined filled, planarized and capped construction where required\u003C/td>\n\u003Ctd>Hole locations, finished pad surface, materials and acceptance criteria; review the actual pad and component with the fabricator and assembler.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>These are starting points for a design review, not interchangeable process names or a guarantee that any particular construction is available for every board. The \u003Ca href=\"/en/blog/via-in-pad-manufacturing\">via-in-pad manufacturing article\u003C/a> goes deeper into filled and capped solderable pads; \u003Ca href=\"/en/blog/what-is-a-via-pcb\">PCB via basics\u003C/a> explains how vias connect layers.\u003C/p>\n\u003Ch2 id=\"what-changes-near-a-component-pad\" data-anchor-en=\"what-changes-near-a-component-pad\">What changes near a component pad?\u003C/h2>\n\u003Cp>Consider a via beside a fine-pitch solder pad. The pad must have the intended mask opening for assembly, while the via may be covered. Review the copper and mask geometry together: a desired separation in the CAD view is useful only if the released mask output and the manufacturing process can produce the intended result. Ask the fabricator to review tight mask features rather than relying on a generic clearance figure.\u003C/p>\n\u003Cp>If a via is inside a soldered pad, the concern is different. An open hole can allow solder to move away from the joint during assembly. Covering a via with mask is not the same as providing the flat solderable surface the pad design may require. Discuss the via-in-pad construction, surface condition and assembly process together before approving the files.\u003C/p>\n\u003Cp>For test access, the opposite may be true: a via deliberately opened on the probe side can be useful. Label it in the test plan and confirm that the test team can actually reach it. A mask opening by itself does not prove electrical test coverage.\u003C/p>\n\u003Ch2 id=\"tenting-plugging-and-filling-what-changes-inside-the-hole\" data-anchor-en=\"tenting-plugging-and-filling-what-changes-inside-the-hole\">Tenting, plugging and filling: what changes inside the hole?\u003C/h2>\n\u003Cp>Think about two independent decisions: what happens at the surface, and what is required inside the via. A mask layer can cover copper on the outside of the board. Plugging introduces material at an opening; the required depth and condition must be agreed for the selected process. Filling addresses the interior of the hole. Capping is another surface construction, which may be specified over a filled via when a solderable pad is needed. A drawing should not use these words as synonyms.\u003C/p>\n\u003Cp>Filling also does not automatically tell the buyer which material is used, whether the surface is planarized, or whether a copper cap is present. If these properties matter, identify them in the drawing and ask for the applicable process and acceptance criteria. Conductive and nonconductive materials are different choices; their suitability depends on their actual properties and the application. A nonconductive fill does not by itself remove the plated copper barrel's electrical connection between layers.\u003C/p>\n\u003Cp>Solder mask is a surface coating, not a substitute for a project-specific sealing specification. A covered via may have an opening or discontinuity that is difficult to determine from a drawing alone. If contamination, cleaning chemistry or moisture is a concern, identify the exposure and required verification with the fabricator and product team. Do not describe a mask-covered via as hermetically sealed merely because the mask file has no opening.\u003C/p>\n\u003Ch2 id=\"a-practical-example-three-via-groups-on-one-board\" data-anchor-en=\"a-practical-example-three-via-groups-on-one-board\">A practical example: three via groups on one board\u003C/h2>\n\u003Cp>Imagine a board with small vias beside an IC footprint, larger vias reserved for a test fixture, and vias inside an exposed thermal pad. The groups do different jobs, so a blanket “tent all vias” instruction loses useful information.\u003C/p>\n\u003Cp>For the vias next to the IC pads, the designer can request mask coverage on the relevant side and ask the fabricator to review the remaining mask between the via and adjacent pad. The fabrication output should still leave the component pads open as intended. The assembler can then review the actual pad and stencil geometry rather than assuming the mask alone will resolve every soldering risk.\u003C/p>\n\u003Cp>For the test locations, identify the accessible side, coordinates and net names. Compare them with the fixture design and any component or enclosure restrictions. A mask opening gives physical exposure; probe contact, electrical coverage and the finished assembly's function need their own verification.\u003C/p>\n\u003Cp>For the thermal-pad vias, provide the component land pattern and the proposed solder-paste pattern to both fabrication and assembly teams. Whether to leave holes open, plug them or use a filled-and-capped construction depends on the package instructions, thermal and electrical requirements, available processes and acceptance criteria. This example describes an engineering review, not a demonstrated APTPCB project or a recommendation to apply one treatment to every thermal via.\u003C/p>\n\u003Ch2 id=\"troubleshoot-a-mismatch-before-it-reaches-assembly\" data-anchor-en=\"troubleshoot-a-mismatch-before-it-reaches-assembly\">Troubleshoot a mismatch before it reaches assembly\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Observation\u003C/th>\n\u003Cth>Question to investigate\u003C/th>\n\u003Cth>Evidence to compare\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>A via intended for a probe is covered\u003C/td>\n\u003Ctd>Was the wrong side or group selected, or did the released mask output differ from the test plan?\u003C/td>\n\u003Ctd>Probe-side coordinates, mask layers, fabrication note and finished-board inspection.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>An opening appears in a group marked “tented”\u003C/td>\n\u003Ctd>Was continuous coverage actually specified and agreed for this hole geometry?\u003C/td>\n\u003Ctd>Finished-hole dimensions, mask output, fabrication requirements and agreed inspection method.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Solder appears to have moved into an exposed hole\u003C/td>\n\u003Ctd>Was the hole intentionally open, and does the package or assembly plan address the potential solder path?\u003C/td>\n\u003Ctd>Component land pattern, via position, stencil data and assembly observations.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>A filled pad is not at the expected surface condition\u003C/td>\n\u003Ctd>Did the drawing specify both the construction and acceptable finished surface?\u003C/td>\n\u003Ctd>Approved fabrication notes, material/process information and the agreed inspection record.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>These observations are diagnostic starting points, not proof of a single root cause. Preserve the affected board and record its revision, location and process history before changing the drawing or reworking the assembly. A cross-section or other examination may be appropriate when agreed by the responsible engineering and quality teams, but the method and sample plan must fit the question being investigated.\u003C/p>\n\u003Ch2 id=\"what-affects-manufacturability-and-cost\" data-anchor-en=\"what-affects-manufacturability-and-cost\">What affects manufacturability and cost?\u003C/h2>\n\u003Cp>Via diameter, board thickness, hole aspect ratio, access from each side, the selected material and the required surface condition all affect the conversation with a fabricator. Tighter or more extensive acceptance requirements may also change inspection and documentation work. The supplier must evaluate the combination; a limit published for one material or process should not be treated as a universal rule or as an APTPCB capability.\u003C/p>\n\u003Cp>When comparing quotations, use the same hole groups, treatment, finished-surface requirements and acceptance criteria. Ask whether any additional process or verification is included and how exceptions will be handled. A quote for ordinary mask coverage and a quote for filled, planarized and capped vias are not necessarily describing the same finished board.\u003C/p>\n\u003Ch2 id=\"example-fabrication-note\" data-anchor-en=\"example-fabrication-note\">Example fabrication note\u003C/h2>\n\u003Cp>The following is an illustrative way to communicate intent, not a substitute for an approved drawing:\u003C/p>\n\u003Cblockquote>\n\u003Cp>Vias in group A: mask-covered on the component side; leave the opposite side as shown in the released mask data. Vias in group B: keep the specified probe-side openings accessible. Vias in group C: submit the proposed hole treatment and finished-surface criteria for approval before fabrication. Identify the affected locations in the drill and drawing package.\u003C/p>\n\u003C/blockquote>\n\u003Cp>Add the applicable drawing revision, acceptance criteria and inspection requirements for the actual project. If a standard is invoked, name its revision and the relevant customer requirements; the fabricator should confirm how the specified construction will be interpreted. Resolve conflicts between notes and exported layers before release, not after a board is built.\u003C/p>\n\u003Ch2 id=\"check-the-output-then-agree-on-the-finished-board-result\" data-anchor-en=\"check-the-output-then-agree-on-the-finished-board-result\">Check the output, then agree on the finished-board result\u003C/h2>\n\u003Cp>Before release, inspect the front and back mask outputs around representative covered and exposed vias, including any exceptions. Confirm that the drill and copper data, mask files and fabrication notes describe the same groups. For example, a test via may need an opening on the bottom while its top side remains covered; put both requirements in the release package rather than relying on an unexplained visual pattern.\u003C/p>\n\u003Cp>When plugging or filling is needed, identify the hole locations and ask the fabricator to confirm the available process, material, inspection and acceptance criteria. Specify any required surface condition separately. A covered appearance is not evidence of fill quality, and the mere word “filled” does not define allowable voids or a finished surface profile.\u003C/p>\n\u003Ch2 id=\"what-should-the-fabrication-note-say\" data-anchor-en=\"what-should-the-fabrication-note-say\">What should the fabrication note say?\u003C/h2>\n\u003Cp>Identify the affected via groups, the required treatment on each side and the locations that must remain accessible. State why any particularly important surface or opening matters, and provide the project-specific inspection or acceptance requirements. Where a standard, revision or customer specification applies, identify it in the purchase documents and resolve any ambiguity with the fabricator.\u003C/p>\n\u003Cp>The \u003Ca href=\"/en/blog/dfm-guidelines-for-pcb-layout\">PCB layout DFM guidelines\u003C/a> cover the wider release package. For a particular design, use the \u003Ca href=\"/en/quote\">quote page\u003C/a> or \u003Ca href=\"/en/contact\">contact APTPCB\u003C/a> to discuss the proposed treatment and the checks needed for it.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/via-in-pad-manufacturing\">via-in-pad manufacturing article\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/what-is-a-via-pcb\">PCB via basics\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/dfm-guidelines-for-pcb-layout\">PCB layout DFM guidelines\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote\">quote page\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/contact\">contact APTPCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26,29,32,35,38,41],{"id":15,"text":16},"what-does-a-tented-via-actually-cover","What does a tented via actually cover?",{"id":18,"text":19},"which-treatment-should-be-specified","Which treatment should be specified?",{"id":21,"text":22},"what-changes-near-a-component-pad","What changes near a component pad?",{"id":24,"text":25},"tenting-plugging-and-filling-what-changes-inside-the-hole","Tenting, plugging and filling: what changes inside the hole?",{"id":27,"text":28},"a-practical-example-three-via-groups-on-one-board","A practical example: three via groups on one board",{"id":30,"text":31},"troubleshoot-a-mismatch-before-it-reaches-assembly","Troubleshoot a mismatch before it reaches assembly",{"id":33,"text":34},"what-affects-manufacturability-and-cost","What affects manufacturability and cost?",{"id":36,"text":37},"example-fabrication-note","Example fabrication note",{"id":39,"text":40},"check-the-output-then-agree-on-the-finished-board-result","Check the output, then agree on the finished-board result",{"id":42,"text":43},"what-should-the-fabrication-note-say","What should the fabrication note say?",[45,46,47,48],"PCB vias","solder mask","PCB fabrication","design for manufacturing","via-tenting-pcb",{"blog":51,"breadcrumb":60,"faq":74},{"@context":52,"@type":53,"headline":4,"description":5,"image":8,"url":54,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":55,"articleSection":7,"author":56,"publisher":59},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/via-tenting-pcb","PCB vias, solder mask, PCB fabrication, design for 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