[{"data":1,"prerenderedAt":398},["ShallowReactive",2],{"blog-what-is-a-via-pcb-en":3,"header-nav-en":75},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tags":13,"slug":21,"jsonld":22},"What Is a Via in a PCB? Types, Sizes and Cost","A PCB via connects copper between layers. Compare through, blind, buried, micro and via-in-pad vias by drill size, aspect ratio, cost and when each fits.","2026-10-01","technology","/assets/img/pcb/advanced-pcb-manufacturing-any-layer-hdi-microsection.webp",16,3187,"PT16M","\u003Cp>A via in a PCB is a small plated hole that connects copper on one layer to copper on another. A circuit board via is sometimes just called a via hole. The hole is drilled, its wall is coated with copper, and the resulting barrel carries a signal, power, or ground from one layer to the next. Vias are what make a multilayer circuit board possible: without them, every trace would have to stay on the layer where it started.\u003C/p>\n\u003Cp>Most boards only need plain through-hole vias. Blind, buried, micro, and via-in-pad structures exist to solve specific density problems, and each one adds drilling, lamination, or plating steps that you pay for. The useful question is not "which via is best" but "what is the cheapest via structure that still lets this layout route?"\u003C/p>\n\u003Cp>This guide explains what vias are, the main types of vias, how via size and aspect ratio limit your choices, and how to call vias out so the fabricator quotes the board you designed.\u003C/p>\n\u003Ch2 id=\"key-takeaways\" data-anchor-en=\"key-takeaways\">Key takeaways\u003C/h2>\n\u003Cul>\n\u003Cli>A PCB via is a plated hole that joins copper on two or more layers. A component hole holds a lead; a via only carries current between layers.\u003C/li>\n\u003Cli>Through vias are the default and the cheapest. Blind, buried, and microvias trade cost for routing space.\u003C/li>\n\u003Cli>Aspect ratio (board thickness divided by drilled hole diameter) sets the smallest through via you can plate reliably on a given board thickness.\u003C/li>\n\u003Cli>Every additional lamination cycle, laser step, or fill-and-cap operation shows up in price and lead time. Count them before you commit to a structure.\u003C/li>\n\u003Cli>Put vias on the fabrication drawing as a drill table by layer pair, with fill, cap, and protection requirements stated, rather than leaving them to CAM interpretation.\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"what-is-a-via-in-a-pcb\" data-anchor-en=\"what-is-a-via-in-a-pcb\">What is a via in a PCB?\u003C/h2>\n\u003Cp>The word comes from the Latin for "path", and some engineers expand it as vertical interconnect access. On a circuit board, a via has three parts:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Part\u003C/th>\n\u003Cth>What it is\u003C/th>\n\u003Cth>Why it matters\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Barrel\u003C/td>\n\u003Ctd>The plated copper wall inside the drilled hole\u003C/td>\n\u003Ctd>Carries the current; its plating thickness and integrity decide reliability\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Pad (land)\u003C/td>\n\u003Ctd>The copper ring around the hole on each connected layer\u003C/td>\n\u003Ctd>Gives the drill a target and the barrel a place to join the trace\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Antipad (clearance)\u003C/td>\n\u003Ctd>The copper-free gap around the barrel on planes it must not touch\u003C/td>\n\u003Ctd>Prevents shorts to planes it passes through and affects impedance\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The ring of copper left between the hole edge and the pad edge is the annular ring. If the drill lands off-center, the ring thins out on one side, which is why drill registration matters as much as hole size.\u003C/p>\n\u003Ch3 id=\"vias-versus-through-holes-for-components\" data-anchor-en=\"vias-versus-through-holes-for-components\">Vias versus through-holes for components\u003C/h3>\n\u003Cp>Both are plated holes, and on a drill file they look alike. The difference is what goes in them. A component hole is sized for a lead or press-fit pin, so its finished diameter and tolerance are set by the part. A via carries no lead, so it can be much smaller, and its job is purely electrical or thermal. Some boards also use non-plated holes for mounting, which are neither.\u003C/p>\n\u003Ch2 id=\"which-via-type-does-your-bga-need-through-blind-micro-or-via-in-pad\" data-anchor-en=\"which-via-type-does-your-bga-need-through-blind-micro-or-via-in-pad\">Which via type does your BGA need: through, blind, micro, or via-in-pad?\u003C/h2>\n\u003Cp>There are four basic via types, plus a few variants built from them. The table summarizes how APT's drilling page describes each structure and how it is produced.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Via type\u003C/th>\n\u003Cth>What it connects\u003C/th>\n\u003Cth>How it is made\u003C/th>\n\u003Cth>Typical reason to use it\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Through via (PTH)\u003C/td>\n\u003Ctd>Top layer to bottom layer, passing every layer\u003C/td>\n\u003Ctd>Mechanical CNC drilling after the final lamination\u003C/td>\n\u003Ctd>Standard signal and power routing\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Blind via\u003C/td>\n\u003Ctd>An outer layer to one or more inner layers, not through the board\u003C/td>\n\u003Ctd>Mechanical controlled-depth or laser drilling\u003C/td>\n\u003Ctd>Fan-out from dense parts, recovering routing space on other layers\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Buried via\u003C/td>\n\u003Ctd>Inner layers only; invisible from the outside\u003C/td>\n\u003Ctd>Mechanical drilling on an inner sub-lamination\u003C/td>\n\u003Ctd>Crossing dense inner routing channels\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Microvia\u003C/td>\n\u003Ctd>One build-up layer to the next\u003C/td>\n\u003Ctd>Laser ablation on a thin dielectric\u003C/td>\n\u003Ctd>HDI structures and fine-pitch BGA escape\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Stacked microvia\u003C/td>\n\u003Ctd>Several microvias directly on top of one another\u003C/td>\n\u003Ctd>Laser ablation with each lower via filled and plated flat\u003C/td>\n\u003Ctd>The densest routing, very fine BGA pitch\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Staggered microvia\u003C/td>\n\u003Ctd>Microvias offset from layer to layer\u003C/td>\n\u003Ctd>Laser ablation\u003C/td>\n\u003Ctd>Density with less stacking, often preferred for thermal cycling\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Via-in-pad (VIPPO)\u003C/td>\n\u003Ctd>A via placed inside an SMD pad, filled and plated over\u003C/td>\n\u003Ctd>Drilling plus fill, planarization, and cap plating\u003C/td>\n\u003Ctd>Fine-pitch BGA breakout without dog-bone traces\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Backdrilled via\u003C/td>\n\u003Ctd>A through via with the unused copper stub drilled away\u003C/td>\n\u003Ctd>Controlled-depth counter-drilling\u003C/td>\n\u003Ctd>Reducing stub reflections on fast serial links\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Thermal via array\u003C/td>\n\u003Ctd>A grid of plated holes under a thermal pad\u003C/td>\n\u003Ctd>Mechanical drilling\u003C/td>\n\u003Ctd>Moving heat from a power device into planes\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Through vias, blind vias, and buried vias are the core vocabulary. Microvias and via-in-pad are where HDI begins. For how blind and buried spans are planned layer by layer, see the \u003Ca href=\"/en/blog/blind-buried-via-planning\">blind and buried via planning guide\u003C/a>.\u003C/p>\n\u003Cp>Most via guides list 4 via types and stop. This section adds the 0.4 mm pitch BGA trigger for switching types, and what stays the same at 0.65 mm or larger.\u003C/p>\n\u003Ch3 id=\"through-vias\" data-anchor-en=\"through-vias\">Through vias\u003C/h3>\n\u003Cp>A through via is drilled after all layers are laminated, so it costs one drilling and one plating pass. It passes every layer, which means it also blocks routing on every layer, even the ones it does not need to connect. On a board with two or three dense packages, that blocking is usually what pushes a design toward blind or buried vias.\u003C/p>\n\u003Ch3 id=\"blind-and-buried-vias\" data-anchor-en=\"blind-and-buried-vias\">Blind and buried vias\u003C/h3>\n\u003Cp>A blind via starts on an outer layer and stops inside the board. A buried via starts and stops inside. Buried vias are drilled and plated on an inner core or sub-stack before it is laminated with the rest of the board, so each buried span normally adds a lamination cycle. Blind vias can be made by controlled-depth mechanical drilling or by laser, depending on depth and diameter.\u003C/p>\n\u003Ch3 id=\"microvias\" data-anchor-en=\"microvias\">Microvias\u003C/h3>\n\u003Cp>A microvia is a small laser-drilled via that spans a single thin dielectric layer. On APT's drilling capability matrix, CO2 laser microvias reach 0.10 mm and UV laser microvias reach 0.075 mm, with a 1:1 aspect ratio per build-up layer. Microvias are the building block of HDI notation such as 1+N+1 (one build-up layer on each side of a core) and 2+N+2 (two build-up layers per side).\u003C/p>\n\u003Ch2 id=\"via-drill-and-aspect-ratio-what-limits-the-smallest-via-you-can-actually-order\" data-anchor-en=\"via-drill-and-aspect-ratio-what-limits-the-smallest-via-you-can-actually-order\">Via drill and aspect ratio: what limits the smallest via you can actually order?\u003C/h2>\n\u003Cp>Via size is limited by two things: how small a hole the factory can drill, and how deep a hole of that size can be plated evenly.\u003C/p>\n\u003Cp>Aspect ratio is the board thickness divided by the drilled hole diameter. A 1.6 mm board with a 0.15 mm drill has an aspect ratio of about 10.7:1. Plating solution has to flow through the full length of the barrel, so a deeper, narrower hole is harder to plate to a uniform copper thickness.\u003C/p>\n\u003Cp>These are the figures APT publishes on its \u003Ca href=\"/en/pcb/pcb-drilling\">PCB drilling capability page\u003C/a>:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Parameter\u003C/th>\n\u003Cth>Mechanical CNC drilling\u003C/th>\n\u003Cth>CO2 laser\u003C/th>\n\u003Cth>UV laser\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Minimum diameter\u003C/td>\n\u003Ctd>0.15 mm (6 mil)\u003C/td>\n\u003Ctd>0.10 mm (4 mil)\u003C/td>\n\u003Ctd>0.075 mm (3 mil)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Maximum diameter\u003C/td>\n\u003Ctd>6.35 mm (250 mil)\u003C/td>\n\u003Ctd>0.20 mm (8 mil)\u003C/td>\n\u003Ctd>0.15 mm (6 mil)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Aspect ratio\u003C/td>\n\u003Ctd>10:1 to 12:1 in standard production; up to 15:1 on validated thick backplanes\u003C/td>\n\u003Ctd>1:1 per build-up layer\u003C/td>\n\u003Ctd>1:1 per build-up layer\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Hole types\u003C/td>\n\u003Ctd>PTH, blind, buried, NPTH, slots\u003C/td>\n\u003Ctd>Blind microvia\u003C/td>\n\u003Ctd>Blind microvia, direct copper\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Those values are capability limits, not design targets. Combining several limits on one board, such as the smallest drill on the thickest stackup, needs a feasibility review against the actual stackup and panel. If your layout has room for a larger via, using it gives the plating process more margin and usually costs less.\u003C/p>\n\u003Cp>Most guides quote a 10:1 aspect ratio as the rule. This one shows the 12:1 to 15:1 range APT validates on small runs, and why the conservative number is conservative.\u003C/p>\n\u003Ch3 id=\"how-to-size-a-through-via\" data-anchor-en=\"how-to-size-a-through-via\">How to size a through via\u003C/h3>\n\u003Cp>Work from the board, not the drill table:\u003C/p>\n\u003Col>\n\u003Cli>Fix the finished board thickness first. It sets the depth every through via has to be plated.\u003C/li>\n\u003Cli>Divide that thickness by the candidate drill size. If the result sits near the top of the supplier's production range, move up a drill size where routing allows.\u003C/li>\n\u003Cli>Add the annular ring the fabricator needs around the drill, then check that the pad still fits your pitch.\u003C/li>\n\u003Cli>If the pad does not fit, that is the point where a blind via, microvia, or via-in-pad becomes worth its cost.\u003C/li>\n\u003C/ol>\n\u003Ch2 id=\"via-in-pad-and-filled-vias\" data-anchor-en=\"via-in-pad-and-filled-vias\">Via-in-pad and filled vias\u003C/h2>\n\u003Cp>Via-in-pad places the via inside the component pad instead of beside it. Open holes in a pad would wick solder away from the joint during reflow, so the via is filled, planarized, and plated over. APT's drilling page lists VIPPO for fine-pitch BGA breakout and solder-wicking prevention, and as the base that lets one microvia be stacked on another.\u003C/p>\n\u003Cp>Filling is not only for via-in-pad. Fill may be specified to keep solder mask or flux out of holes, to give a flat surface for assembly, or to support a stacked microvia. Fill material can be conductive or non-conductive, and the choice should be recorded on the drawing. For the process controls and acceptance points, see the \u003Ca href=\"/en/blog/via-in-pad-manufacturing\">via-in-pad manufacturing guide\u003C/a> and the article on \u003Ca href=\"/en/blog/void-control-for-vippo-bga\">void control for VIPPO under BGAs\u003C/a>.\u003C/p>\n\u003Cp>Via protection (tenting, plugging, or filling with or without a cap) is classified in IPC-4761. Name the protection method you want on the drawing. "Tented" alone leaves room for interpretation.\u003C/p>\n\u003Ch2 id=\"choosing-a-via-structure-cost-and-lamination-count\" data-anchor-en=\"choosing-a-via-structure-cost-and-lamination-count\">Choosing a via structure: cost and lamination count\u003C/h2>\n\u003Cp>This is the decision table. Start in the top row and move down only when the layout forces you to. Relative cost is a ranking for the same board size and layer count, not a price.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Via structure\u003C/th>\n\u003Cth>Drilling steps\u003C/th>\n\u003Cth>Extra lamination cycles\u003C/th>\n\u003Cth>Relative cost\u003C/th>\n\u003Cth>Move to it when\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Through vias only\u003C/td>\n\u003Ctd>One mechanical pass\u003C/td>\n\u003Ctd>None\u003C/td>\n\u003Ctd>Lowest\u003C/td>\n\u003Ctd>Default; every net can escape with through vias\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Through + mechanical blind (controlled depth)\u003C/td>\n\u003Ctd>Mechanical plus depth-controlled pass\u003C/td>\n\u003Ctd>Usually none\u003C/td>\n\u003Ctd>Low to moderate\u003C/td>\n\u003Ctd>A few outer-to-inner connections free up a congested layer\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Through + buried\u003C/td>\n\u003Ctd>Mechanical on sub-stack, then final\u003C/td>\n\u003Ctd>One per buried span\u003C/td>\n\u003Ctd>Moderate\u003C/td>\n\u003Ctd>Inner channels are blocked, but outer layers are not\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>1+N+1 HDI (one microvia layer per side)\u003C/td>\n\u003Ctd>Laser plus mechanical\u003C/td>\n\u003Ctd>One build-up cycle\u003C/td>\n\u003Ctd>Moderate to high\u003C/td>\n\u003Ctd>BGA pitch is too fine for through-via fan-out\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>2+N+2 HDI (staggered or stacked)\u003C/td>\n\u003Ctd>Two laser steps per side plus mechanical\u003C/td>\n\u003Ctd>Two build-up cycles\u003C/td>\n\u003Ctd>High\u003C/td>\n\u003Ctd>One microvia layer still does not escape the package\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Via-in-pad (filled and capped)\u003C/td>\n\u003Ctd>Adds fill, planarization, cap plating\u003C/td>\n\u003Ctd>None by itself\u003C/td>\n\u003Ctd>Adds to any of the above\u003C/td>\n\u003Ctd>Dog-bone fan-out does not fit between pads\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Backdrill\u003C/td>\n\u003Ctd>Adds controlled-depth counter-drill\u003C/td>\n\u003Ctd>None\u003C/td>\n\u003Ctd>Adds to any of the above\u003C/td>\n\u003Ctd>Stub length hurts a fast channel\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Two rules keep this table honest:\u003C/p>\n\u003Cul>\n\u003Cli>Count lamination cycles. Each one adds pressing, drilling registration, and inspection time. APT's HDI pages note that a 2+N+2 build adds lamination, registration, plating, inspection, cost, and schedule compared with 1+N+1.\u003C/li>\n\u003Cli>Do not mix structures casually. A board with buried vias, stacked microvias, and backdrilling has three separate process risks. If one structure can solve the routing alone, use one.\u003C/li>\n\u003C/ul>\n\u003Cp>APT's rigid PCB capability page notes that fine-pitch BGAs around 0.4 mm or 0.5 mm, tight routing channels, or high-speed layer transitions that cannot be achieved with through vias are the usual triggers for an HDI build. When that is your situation, the \u003Ca href=\"/en/pcb/hdi-pcb\">HDI PCB manufacturing\u003C/a> team can review whether a 1+N+1 structure is enough before you design for 2+N+2.\u003C/p>\n\u003Ch3 id=\"when-vias-affect-signal-integrity\" data-anchor-en=\"when-vias-affect-signal-integrity\">When vias affect signal integrity\u003C/h3>\n\u003Cp>At high data rates the via is part of the transmission line. The unused part of a through via below the last connected layer, the stub, can reflect energy. Options are to route the fast signal to a layer near the bottom, use a blind via, or backdrill the stub. APT publishes a backdrill depth accuracy of ±50 μm. The \u003Ca href=\"/en/blog/backdrill-planning-guide\">backdrill planning guide\u003C/a> covers how to define depth and stub targets.\u003C/p>\n\u003Ch3 id=\"thermal-vias\" data-anchor-en=\"thermal-vias\">Thermal vias\u003C/h3>\n\u003Cp>Thermal via arrays move heat from an exposed pad into internal planes. They are ordinary through vias in a grid, but they create a solder-wicking problem under bottom-terminated packages. Decide early whether they will be filled, plugged, or left open with a paste-reduction pattern on the stencil.\u003C/p>\n\u003Ch2 id=\"how-vias-drive-pcb-cost\" data-anchor-en=\"how-vias-drive-pcb-cost\">How vias drive PCB cost\u003C/h2>\n\u003Cp>Beyond the structure itself, three via choices move the quote: total drill count (machine time), the smallest mechanical drill (tool wear and drill stack height), and aspect ratio near the top of the supplier's range (slower plating or extra cross-section checks). Microsection coupons for via structures add inspection scope when the order calls for them.\u003C/p>\n\u003Cp>If the quote is higher than expected, ask the fabricator which via feature is driving it. Often one package forced the whole board into HDI, and moving or swapping that part removes a lamination cycle.\u003C/p>\n\u003Ch2 id=\"via-callouts-on-the-fab-drawing\" data-anchor-en=\"via-callouts-on-the-fab-drawing\">Via callouts on the fab drawing\u003C/h2>\n\u003Cp>A clear callout is the cheapest way to avoid a wrong build. Include:\u003C/p>\n\u003Cul>\n\u003Cli>A drill table by layer pair, for example L1–L2 laser, L2–L7 buried, L1–L8 through, with finished or drilled sizes stated and which one is which\u003C/li>\n\u003Cli>Plated versus non-plated holes, separated in the NC drill files\u003C/li>\n\u003Cli>Via fill requirement and material (conductive or non-conductive), and whether a cap is required\u003C/li>\n\u003Cli>Via protection method by IPC-4761 type where used, and on which side\u003C/li>\n\u003Cli>Via-in-pad locations, if any, and the flatness or dimple expectation for those pads\u003C/li>\n\u003Cli>Backdrill locations, the layer that must stay connected, and the allowed stub\u003C/li>\n\u003Cli>The acceptance class for the board, for example IPC-6012 Class 2 or Class 3\u003C/li>\n\u003C/ul>\n\u003Cp>APT's HDI capability page asks for the proposed stackup, a layer-to-layer via map, stacked or staggered callouts, buried vias, and via-in-pad locations with the RFQ. Sending those with Gerber X2, ODB++, or IPC-2581 data lets CAM confirm the structure instead of guessing it.\u003C/p>\n\u003Ch2 id=\"why-involve-aptpcb-in-via-planning\" data-anchor-en=\"why-involve-aptpcb-in-via-planning\">Why involve APTPCB in via planning?\u003C/h2>\n\u003Cp>APT reviews via structures as part of the engineering check before fabrication release. The review compares the via map with the stackup, finished thickness, drill sizes, and aspect ratio, then flags combinations that sit at the edge of the \u003Ca href=\"/en/capabilities/hdi-pcb\">HDI capability range\u003C/a> or that could be simplified. Final via diameter, aspect ratio, capture pad, and sequential-lamination feasibility are confirmed only after that review, because they depend on the complete material, stackup, panel, and quantity.\u003C/p>\n\u003Cp>Relevant standards and references may include:\u003C/p>\n\u003Cul>\n\u003Cli>IPC-2221: generic standard on printed board design\u003C/li>\n\u003Cli>IPC-2226: sectional design standard for HDI printed boards\u003C/li>\n\u003Cli>IPC-6012: qualification and performance of rigid printed boards\u003C/li>\n\u003Cli>IPC-4761: design guide for protection of printed board via structures\u003C/li>\n\u003Cli>IPC-A-600: acceptability of printed boards\u003C/li>\n\u003C/ul>\n\u003C!-- faq:start -->\n\u003Ch2 id=\"frequently-asked-questions\" data-anchor-en=\"frequently-asked-questions\">Frequently asked questions\u003C/h2>\n\u003Ch3 id=\"what-are-vias-in-a-pcb-used-for\" data-anchor-en=\"what-are-vias-in-a-pcb-used-for\">What are vias in a PCB used for?\u003C/h3>\n\u003Cp>Vias in a PCB carry a signal, power, or ground connection from one copper layer to another through a plated hole. It lets traces change layers, ties planes together, and in arrays it can move heat from a component into internal copper.\u003C/p>\n\u003Ch3 id=\"what-are-the-main-types-of-vias\" data-anchor-en=\"what-are-the-main-types-of-vias\">What are the main types of vias?\u003C/h3>\n\u003Cp>The main types of vias are through vias, blind vias, buried vias, and microvias. Variants built on these include stacked and staggered microvias, via-in-pad (filled and capped), backdrilled vias, and thermal via arrays.\u003C/p>\n\u003Ch3 id=\"what-is-the-smallest-via-size-a-pcb-can-have\" data-anchor-en=\"what-is-the-smallest-via-size-a-pcb-can-have\">What is the smallest via size a PCB can have?\u003C/h3>\n\u003Cp>It depends on how the hole is made. APT publishes 0.15 mm as the minimum mechanical drill, 0.10 mm for CO2 laser microvias, and 0.075 mm for UV laser microvias. The usable size on a specific board also depends on its thickness, stackup, and pad size.\u003C/p>\n\u003Ch3 id=\"what-is-the-difference-between-a-blind-via-and-a-buried-via\" data-anchor-en=\"what-is-the-difference-between-a-blind-via-and-a-buried-via\">What is the difference between a blind via and a buried via?\u003C/h3>\n\u003Cp>A blind via starts on an outer layer and ends on an inner layer, so you can see it from one side. A buried via connects inner layers only and is not visible from either surface. Buried vias usually add a lamination cycle because they are drilled before the final press.\u003C/p>\n\u003Ch3 id=\"do-vias-increase-pcb-cost\" data-anchor-en=\"do-vias-increase-pcb-cost\">Do vias increase PCB cost?\u003C/h3>\n\u003Cp>Through vias add little beyond drill time. Blind, buried, laser, filled, capped, and backdrilled vias each add process steps, and HDI build-up layers add lamination cycles. The structure matters more than the number of holes.\u003C/p>\n\u003Ch3 id=\"can-you-put-a-via-in-a-pad\" data-anchor-en=\"can-you-put-a-via-in-a-pad\">Can you put a via in a pad?\u003C/h3>\n\u003Cp>Yes, but an open via in a pad will draw solder away from the joint. For BGA and fine-pitch pads, the via is normally filled, planarized, and plated over (VIPPO) so the pad is flat and solderable.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Ch2 id=\"via-rfq-checklist\" data-anchor-en=\"via-rfq-checklist\">Via RFQ checklist\u003C/h2>\n\u003Cul>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Minimum mechanical drill size required\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Minimum laser drill size and type: CO2 or UV laser\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Aspect ratio (AR) of the deepest through via\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Via type by layer pair: through, blind, buried, microvia, via-in-pad\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Via fill requirement: conductive, non-conductive, or copper overfilled\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Via protection method: tented, plugged, or filled by IPC-4761 type\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Backdrill required: Y/N; target depth and depth tolerance ( ±50 µm)\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Interference-fit press-fit pin hole size and tolerance if applicable\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> HDI structure: 1+N+1, 2+N+2, or other sequential lamination\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> IPC-6012 acceptance class for the board\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Impedance-controlled nets with target impedance and tolerance\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Backdrill drill table: layer pair, stub length target, allowed residual\u003C/li>\n\u003C/ul>\n\u003Cp>Use this when you request a quote from a board house.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"picking-the-simplest-via-that-routes\" data-anchor-en=\"picking-the-simplest-via-that-routes\">Picking the simplest via that routes\u003C/h2>\n\u003Cp>Start with through vias and a sensible drill size for your board thickness. Add a structure only when a specific package or channel cannot route without it, and count the lamination cycles each step adds. Then put the result on the drawing as a drill table and a via map. That gives the fabricator what it needs to quote the board you designed, and it gives you a clear place to cut cost if the first quote comes back high.\u003C/p>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/blind-buried-via-planning\">blind and buried via planning guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb/pcb-drilling\">PCB drilling capability page\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/via-in-pad-manufacturing\">via-in-pad manufacturing guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/void-control-for-vippo-bga\">void control for VIPPO under BGAs\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb/hdi-pcb\">HDI PCB manufacturing\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/backdrill-planning-guide\">backdrill planning guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/capabilities/hdi-pcb\">HDI capability range\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,15,16,17,18,19,20],"PCB Via","Vias","What Is a Via","Types of Vias","Via Hole PCB","Blind and Buried Vias","Via-in-Pad","what-is-a-via-pcb",{"blog":23,"breadcrumb":32,"faq":46},{"@context":24,"@type":25,"headline":4,"description":5,"image":8,"url":26,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":27,"articleSection":7,"author":28,"publisher":31},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/what-is-a-via-pcb","PCB Via, Vias, What Is a Via, Types of Vias, Via Hole PCB, Blind and Buried Vias, Via-in-Pad",{"@type":29,"name":30},"Organization","APTPCB",{"@type":29,"name":30},{"@context":24,"@type":33,"itemListElement":34},"BreadcrumbList",[35,40,44],{"@type":36,"position":37,"name":38,"item":39},"ListItem",1,"Home","https://aptpcb.com/",{"@type":36,"position":41,"name":42,"item":43},2,"Blog","https://aptpcb.com/en/blog",{"@type":36,"position":45,"name":21,"item":26},3,{"@context":24,"@type":47,"mainEntity":48},"FAQPage",[49,55,59,63,67,71],{"@type":50,"name":51,"acceptedAnswer":52},"Question","What are vias in a PCB used for?",{"@type":53,"text":54},"Answer","Vias in a PCB carry a signal, power, or ground connection from one copper layer to another through a plated hole. It lets traces change layers, ties planes together, and in arrays it can move heat from a component into internal copper.",{"@type":50,"name":56,"acceptedAnswer":57},"What are the main types of vias?",{"@type":53,"text":58},"The main types of vias are through vias, blind vias, buried vias, and microvias. Variants built on these include stacked and staggered microvias, via-in-pad (filled and capped), backdrilled vias, and thermal via arrays.",{"@type":50,"name":60,"acceptedAnswer":61},"What is the smallest via size a PCB can have?",{"@type":53,"text":62},"It depends on how the hole is made. APT publishes 0.15 mm as the minimum mechanical drill, 0.10 mm for CO2 laser microvias, and 0.075 mm for UV laser microvias. The usable size on a specific board also depends on its thickness, stackup, and pad size.",{"@type":50,"name":64,"acceptedAnswer":65},"What is the difference between a blind via and a buried via?",{"@type":53,"text":66},"A blind via starts on an outer layer and ends on an inner layer, so you can see it from one side. A buried via connects inner layers only and is not visible from either surface. Buried vias usually add a lamination cycle because they are drilled before the final press.",{"@type":50,"name":68,"acceptedAnswer":69},"Do vias increase PCB cost?",{"@type":53,"text":70},"Through vias add little beyond drill time. Blind, buried, laser, filled, capped, and backdrilled vias each add process steps, and HDI build-up layers add lamination cycles. The structure matters more than the number of holes.",{"@type":50,"name":72,"acceptedAnswer":73},"Can you put a via in a pad?",{"@type":53,"text":74},"Yes, but an open via in a pad will draw solder away from the joint. For BGA and fine-pitch pads, the via is normally filled, planarized, and plated over (VIPPO) so the pad is flat and solderable.",{"pcbManufacturingColumns":76,"capabilityColumns":201,"resourceColumns":232,"pcbaColumns":273},[77,125,154,183],{"heading":78,"links":79},"PCB Product Families",[80,83,86,89,92,95,98,101,104,107,110,113,116,119,122],{"label":81,"path":82},"FR-4 PCB","/pcb/fr4-pcb",{"label":84,"path":85},"High-Speed PCB","/pcb/high-speed-pcb",{"label":87,"path":88},"Multilayer PCB","/pcb/multilayer-pcb",{"label":90,"path":91},"HDI PCB","/pcb/hdi-pcb",{"label":93,"path":94},"Flexible PCB","/pcb/flex-pcb",{"label":96,"path":97},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":99,"path":100},"Ceramic PCB","/pcb/ceramic-pcb",{"label":102,"path":103},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":105,"path":106},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":108,"path":109},"Antenna PCB","/pcb/antenna-pcb",{"label":111,"path":112},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":114,"path":115},"Microwave PCB","/pcb/microwave-pcb",{"label":117,"path":118},"Metal Core PCB","/pcb/metal-core-pcb",{"label":120,"path":121},"High-Tg PCB","/pcb/high-tg-pcb",{"label":123,"path":124},"Backplane PCB","/pcb/backplane-pcb",{"sections":126},[127],{"heading":128,"links":129},"RF & Materials",[130,133,136,139,142,145,148,151],{"label":131,"path":132},"Rogers PCB","/materials/rf-rogers",{"label":134,"path":135},"Taconic PCB","/materials/taconic-pcb",{"label":137,"path":138},"Teflon PCB","/materials/teflon-pcb",{"label":140,"path":141},"Arlon PCB","/materials/arlon-pcb",{"label":143,"path":144},"Megtron PCB","/materials/megtron-pcb",{"label":146,"path":147},"ISOLA PCB","/materials/isola-pcb",{"label":149,"path":150},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":152,"path":153},"Impedance Control","/pcb/pcb-impedance-control",{"sections":155},[156],{"heading":157,"links":158},"Manufacturing / Stackups",[159,162,165,168,171,174,177,180],{"label":160,"path":161},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":163,"path":164},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":166,"path":167},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":169,"path":170},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":172,"path":173},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":175,"path":176},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":178,"path":179},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":181,"path":182},"Multi-Layer Laminated Structure","/pcb/multilayer-pcb-lamination-services",{"heading":184,"links":185},"Specialties & Resources",[186,189,192,195,198],{"label":187,"path":188},"PCB Surface Finishes (ENIG / ENEPIG / HASL / OSP / Immersion)","/pcb/pcb-surface-finishes",{"label":190,"path":191},"Drilling & Vias (Blind / Buried / Via-in-Pad / Backdrill / Half Hole)","/pcb/pcb-drilling",{"label":193,"path":194},"PCB Stackup (Standard / High-Layer / Flex / Rigid-Flex / Aluminum)","/pcb/pcb-stack-up",{"label":196,"path":197},"Profiles (Milling / V-Scoring / Depaneling)","/pcb/pcb-profiling",{"label":199,"path":200},"Quality & Inspection (AOI + X-Ray / Flying Probe / PCB DFM Check)","/pcb/pcb-quality",[202,207,212,217,222,227],{"links":203},[204],{"label":205,"path":206},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":208},[209],{"label":210,"path":211},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":213},[214],{"label":215,"path":216},"Flex PCB Capability","/capabilities/flex-pcb",{"links":218},[219],{"label":220,"path":221},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":223},[224],{"label":225,"path":226},"Metal PCB Capability","/capabilities/metal-pcb",{"links":228},[229],{"label":230,"path":231},"Ceramic PCB Capability","/capabilities/ceramic-pcb",[233,244,265],{"heading":234,"links":235},"Downloads",[236,239,242],{"label":237,"path":238},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":240,"path":241},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":181,"path":243},"/pcb/multi-layer-laminated-structure",{"heading":245,"links":246},"Tools",[247,250,253,256,259,262],{"label":248,"path":249},"Gerber Viewer","/tools/gerber-viewer",{"label":251,"path":252},"PCB Viewer","/tools/pcb-viewer",{"label":254,"path":255},"BOM Viewer","/tools/bom-viewer",{"label":257,"path":258},"3D Viewer","/tools/3d-viewer",{"label":260,"path":261},"Circuit Simulator","/tools/circuit-simulator",{"label":263,"path":264},"Impedance Calculator","/tools/impedance-calculator",{"heading":266,"links":267},"FAQ & Blog",[268,271],{"label":269,"path":270},"FAQ","/resources/faq",{"label":42,"path":272},"/blog",[274,304,328,361],{"heading":275,"links":276},"Core Services",[277,280,283,286,289,292,295,298,301],{"label":278,"path":279},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":281,"path":282},"NPI & Small Batch PCB Assembly","/pcba/npi-assembly",{"label":284,"path":285},"Mass Production PCB Assembly","/pcba/mass-production",{"label":287,"path":288},"Flex & Rigid-Flex PCB Assembly","/pcba/flex-rigid-flex",{"label":290,"path":291},"SMT & Through-Hole Assembly","/pcba/smt-tht",{"label":293,"path":294},"BGA PCB Assembly","/pcba/bga-qfn-fine-pitch",{"label":296,"path":297},"Components & BOM Management","/pcba/components-bom",{"label":299,"path":300},"Box Build Assembly","/pcba/box-build-assembly",{"label":302,"path":303},"PCB Assembly Testing & Quality","/pcba/testing-quality",{"heading":305,"links":306},"Supporting Services",[307,310,313,316,319,322,325],{"label":308,"path":309},"Every Support Touchpoint","/pcba/support-services",{"label":311,"path":312},"Stencil Lab","/pcba/pcb-stencil",{"label":314,"path":315},"Components Sourcing","/pcba/component-sourcing",{"label":317,"path":318},"IC Programming","/pcba/ic-programming",{"label":320,"path":321},"Conformal Coating","/pcba/pcb-conformal-coating",{"label":323,"path":324},"Selective Soldering","/pcba/pcb-selective-soldering",{"label":326,"path":327},"BGA Reballing","/pcba/bga-reballing",{"heading":329,"links":330},"Quality & Testing",[331,334,337,340,343,346,349,352,355,358],{"label":332,"path":333},"Quality Inspection","/pcba/quality-system",{"label":335,"path":336},"First Article Inspection (FAI)","/pcba/first-article-inspection",{"label":338,"path":339},"Solder Paste Inspection (SPI)","/pcba/spi-inspection",{"label":341,"path":342},"AOI Optical Inspection","/pcba/aoi-inspection",{"label":344,"path":345},"X-Ray / CT Inspection","/pcba/xray-inspection",{"label":347,"path":348},"ICT In-Circuit Testing","/pcba/ict-test",{"label":350,"path":351},"Flying Probe Testing","/pcba/flying-probe-testing",{"label":353,"path":354},"FCT / Functional Testing","/pcba/fct-test",{"label":356,"path":357},"Final Inspection & Packing","/pcba/final-quality-inspection",{"label":359,"path":360},"Incoming Quality Control","/pcba/incoming-quality-control",{"heading":362,"linkClass":363,"links":364},"Industry Applications (Entry)","text-nowrap",[365,368,371,374,377,380,383,386,389,392,395],{"label":366,"path":367},"Server / Data Center","/industries/server-data-center-pcb",{"label":369,"path":370},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":372,"path":373},"Medical","/industries/medical-pcb",{"label":375,"path":376},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":378,"path":379},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":381,"path":382},"Drone / UAV","/industries/drone-uav-pcb",{"label":384,"path":385},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":387,"path":388},"Power & New Energy","/industries/power-energy-pcb",{"label":390,"path":391},"Robotics & Automation","/industries/robotics-pcb",{"label":393,"path":394},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":396,"path":397},"PCB Industry Overview →","/pcb-industry-solutions",1791013421695]