[{"data":1,"prerenderedAt":398},["ShallowReactive",2],{"blog-what-is-bga-en":3,"header-nav-en":75},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"tags":13,"slug":21,"jsonld":22},"What Is BGA? Ball Grid Array Packages and Soldering","BGA means ball grid array. Learn BGA package types, solder balls, LGA vs BGA, how BGAs are soldered and X-ray inspected, and what they demand of the PCB.","2026-10-01","technology","/assets/img/pcba/xray-bga.webp",19,3637,"PT19M","\u003Cp>BGA stands for ball grid array. A BGA is an integrated circuit package that connects to the circuit board through a grid of small solder balls on its underside instead of leads around its edges. During assembly the balls melt in the reflow oven and become the solder joints between the chip and the PCB.\u003C/p>\n\u003Cp>Because the whole underside is used for connections, a BGA chip can carry far more I/O in a small footprint than a leaded package of the same size. That is why processors, FPGAs, memory, and many SoCs come as BGAs. The trade-off is that every joint is hidden under the package. You cannot see or touch them after reflow, which changes how the board is designed, soldered, inspected, and repaired.\u003C/p>\n\u003Cp>This guide covers what BGA means, the common BGA package types, how a BGA compares with LGA and QFN, and what a BGA asks of the PCB and the assembly line.\u003C/p>\n\u003Ch2 id=\"key-takeaways\" data-anchor-en=\"key-takeaways\">Key takeaways\u003C/h2>\n\u003Cul>\n\u003Cli>BGA meaning: ball grid array, a surface-mount package with solder balls in a grid under the body.\u003C/li>\n\u003Cli>Common BGA package types include plastic BGA (PBGA), flip-chip BGA (FCBGA), ceramic BGA, and chip-scale packages (CSP). They differ mostly in pitch, body size, and how the die is attached inside.\u003C/li>\n\u003Cli>A finer ball pitch means less room between pads for vias and traces. Below a certain pitch, through-via fan-out stops working and the board needs microvias or via-in-pad.\u003C/li>\n\u003Cli>BGA soldering is done by reflow. The balls collapse onto printed paste and self-center by surface tension.\u003C/li>\n\u003Cli>BGA joints are checked with X-ray, not optical AOI. Rework means removing the part, cleaning the site, and replacing or reballing the package.\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"bga-vs-qfn-vs-lga-which-package-fits-your-thermal-and-routing-budget\" data-anchor-en=\"bga-vs-qfn-vs-lga-which-package-fits-your-thermal-and-routing-budget\">BGA vs QFN vs LGA: which package fits your thermal and routing budget?\u003C/h2>\n\u003Cp>Most BGA guides stop at describing the package. This one maps pitch to fan-out structure with stackup triggers, because the board decision drives the cost more than the chip choice.\u003C/p>\n\u003Cp>The three packages look similar in a schematic symbol. In practice they set very different requirements for the PCB. Here is the comparison that decides which package goes on the board.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Aspect\u003C/th>\n\u003Cth>BGA\u003C/th>\n\u003Cth>QFN\u003C/th>\n\u003Cth>LGA\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Thermal path\u003C/td>\n\u003Ctd>bottom + lid\u003C/td>\n\u003Ctd>bottom only\u003C/td>\n\u003Ctd>bottom only\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Pitch floor\u003C/td>\n\u003Ctd>0.3 mm\u003C/td>\n\u003Ctd>0.4 mm\u003C/td>\n\u003Ctd>0.5 mm\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Inspection\u003C/td>\n\u003Ctd>X-ray mandatory\u003C/td>\n\u003Ctd>AOI mostly\u003C/td>\n\u003Ctd>AOI mostly\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Rework cycles\u003C/td>\n\u003Ctd>≤ 3 per APTPCB process\u003C/td>\n\u003Ctd>1–2\u003C/td>\n\u003Ctd>1–2\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Cost to board\u003C/td>\n\u003Ctd>higher\u003C/td>\n\u003Ctd>lower\u003C/td>\n\u003Ctd>similar to BGA\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Inspection skill\u003C/td>\n\u003Ctd>specialist\u003C/td>\n\u003Ctd>normal line\u003C/td>\n\u003Ctd>normal line\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>If the part is available in both BGA and QFN at the same pin count, the QFN is usually the cheaper board. If the part only comes as a BGA, the pitch sets the board cost — and the pitch decision starts with the table below.\u003C/p>\n\u003Ch2 id=\"what-is-inside-a-bga-die-substrate-balls-lid-and-underfill\" data-anchor-en=\"what-is-inside-a-bga-die-substrate-balls-lid-and-underfill\">What is inside a BGA: die, substrate, balls, lid, and underfill\u003C/h2>\n\u003Cp>A BGA has three structural layers. The silicon die sits on top, a small substrate in the middle routes the die's connections out to the ball grid, and the solder balls on the bottom make the board connection.\u003C/p>\n\u003Cp>On a plastic BGA (PBGA), the die is wire-bonded to the substrate through small holes in the substrate and the whole assembly is overmolded in epoxy. On a flip-chip BGA (FCBGA), the die is turned face-down and bonded to the substrate with solder bumps — this shortens the electrical path and is the construction used for CPUs, GPUs, and FPGAs where signal speed matters.\u003C/p>\n\u003Cp>Ceramic BGAs (CBGA) use a ceramic substrate instead of organic material. The higher rigidity and thermal mass make them harder to rework, but the package is more resistant to moisture ingress and is still found on legacy and high-reliability designs.\u003C/p>\n\u003Cp>Chip-scale packages (CSP) push the package size close to the die size, which means small balls at fine pitch and very little rework margin.\u003C/p>\n\u003Ch3 id=\"what-are-bga-balls-made-of\" data-anchor-en=\"what-are-bga-balls-made-of\">What are BGA balls made of?\u003C/h3>\n\u003Cp>BGA balls are solder spheres, usually a lead-free tin-silver-copper (SAC) alloy on current parts, with tin-lead still found on some legacy and high-reliability components. The alloy, ball diameter, and pitch are all on the package drawing. You need all three to design the footprint, the stencil, and to plan reballing if the part ever needs it.\u003C/p>\n\u003Ch3 id=\"thermal-and-mechanical-variants\" data-anchor-en=\"thermal-and-mechanical-variants\">Thermal and mechanical variants\u003C/h3>\n\u003Cp>Some BGAs add a heat spreader or lid on top to improve thermal dissipation from the die. The lid is usually soldered or glued to the substrate and acts as the primary thermal path out of the package. When the datasheet specifies a thermal resistance junction-to-case (θJC), the measurement is to the lid or top of the package.\u003C/p>\n\u003Cp>Underfill is an epoxy dispensed under the BGA body after reflow. It fills the gap between the die, substrate, and board, reduces stress on the solder joints during thermal cycling, and is common on large FCBGAs and boards that see wide temperature swings.\u003C/p>\n\u003Ch2 id=\"when-does-bga-pitch-force-via-in-pad-instead-of-through-via-fan-out\" data-anchor-en=\"when-does-bga-pitch-force-via-in-pad-instead-of-through-via-fan-out\">When does BGA pitch force via-in-pad instead of through-via fan-out?\u003C/h2>\n\u003Cp>Most BGA guides treat via-in-pad as one technique. This one shows when through-via still works at 0.65 mm pitch, and when stacked microvia becomes mandatory at 0.3 mm.\u003C/p>\n\u003Cp>Fan-out is how signals escape the BGA pad grid and reach the rest of the board. It is where most of a BGA's PCB cost is decided.\u003C/p>\n\u003Ch3 id=\"the-pitch-to-stackup-decision-table\" data-anchor-en=\"the-pitch-to-stackup-decision-table\">The pitch-to-stackup decision table\u003C/h3>\n\u003Cp>Use this table to identify what the BGA pitch actually requires from the board before you release the layout.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>BGA pitch\u003C/th>\n\u003Cth>Standard fan-out\u003C/th>\n\u003Cth>Trigger to switch\u003C/th>\n\u003Cth>Minimum board\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>1.0 mm\u003C/td>\n\u003Ctd>Through-via 0.30 mm — fits mechanical limit\u003C/td>\n\u003Ctd>—\u003C/td>\n\u003Ctd>4-layer standard\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>0.8 mm\u003C/td>\n\u003Ctd>Through-via 0.25 mm — at mechanical limit\u003C/td>\n\u003Ctd>—\u003C/td>\n\u003Ctd>4-layer 1+N+1\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>0.65 mm\u003C/td>\n\u003Ctd>Through-via 0.20 mm — below mechanical limit\u003C/td>\n\u003Ctd>Fine-pitch routability tight\u003C/td>\n\u003Ctd>6-layer 2+N+2\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>0.5 mm\u003C/td>\n\u003Ctd>Microvia 0.10 mm CO₂ laser\u003C/td>\n\u003Ctd>Via fan-out starts to crowd\u003C/td>\n\u003Ctd>6-layer 2+N+2\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>0.4 mm\u003C/td>\n\u003Ctd>Via-in-pad mandatory\u003C/td>\n\u003Ctd>Staggered microvia if >2 rows\u003C/td>\n\u003Ctd>8-layer 2+N+2\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>0.3 mm\u003C/td>\n\u003Ctd>Via-in-pad mandatory\u003C/td>\n\u003Ctd>Stacked microvia, ±25 µm placement\u003C/td>\n\u003Ctd>8-layer 2+N+3\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>\u003Cstrong>Data basis:\u003C/strong> APTPCB mechanical drill minimum 0.15 mm (pcb-drilling.json); CO₂ laser microvia 0.10 mm; UV laser microvia 0.075 mm; standard production aspect ratio 10:1–12:1, up to 15:1 for aerospace (pcb-drilling.json); HDI build-ups 1+N+1 and 2+N+2 (hdi-pcb.json); 4–32 layer rigid range (hdi-pcb.json); multi-layer structures 4–18 layers 0.4–2.4 mm (multi-layer-laminated-structure.json).\u003C/p>\n\u003Cp>The 0.4 mm row is the most common trigger point in practice. At 1.6 mm board thickness, a 0.20 mm through-via needed for fan-out at 0.65 mm BGA pitch sits at a 7.5:1 aspect ratio — within the 10:1 standard production limit but with reduced plating margin. Most fabricators recommend moving to a microvia structure before that boundary is reached.\u003C/p>\n\u003Ch3 id=\"the-specific-number-that-changes-the-board\" data-anchor-en=\"the-specific-number-that-changes-the-board\">The specific number that changes the board\u003C/h3>\n\u003Cp>At 0.4 mm BGA pitch, dog-bone fan-out on a 1.6 mm board requires a 0.20 mm drill. The APTPCB mechanical drill floor is 0.15 mm, which means the drill is at the practical limit for reliable plating on a 1.6 mm board (7.5:1 aspect ratio). For a 2.0 mm or 2.4 mm board at the same pitch, the aspect ratio pushes toward or past 12:1. The path that avoids this is via-in-pad with 0.075 mm UV laser microvias on a 2+N+2 HDI stackup — which is why 0.4 mm is the typical trigger for HDI review in the APTPCB process.\u003C/p>\n\u003Ch3 id=\"pad-design-smd-vs-nsmd-and-why-aptpcb-defaults-to-nsmd-for-bgas\" data-anchor-en=\"pad-design-smd-vs-nsmd-and-why-aptpcb-defaults-to-nsmd-for-bgas\">Pad design: SMD vs NSMD and why APTPCB defaults to NSMD for BGAs\u003C/h3>\n\u003Cp>BGA pads on the PCB are either solder-mask defined (SMD) or non-solder-mask defined (NSMD). The choice affects pad stress, solder joint reliability, and how much registration tolerance the solder mask can absorb.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Feature\u003C/th>\n\u003Cth>SMD (Solder Mask Defined)\u003C/th>\n\u003Cth>NSMD (Non-Solder Mask Defined)\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Pad definition\u003C/td>\n\u003Ctd>Solder mask opening is smaller than copper pad\u003C/td>\n\u003Ctd>Copper pad is smaller than mask opening\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Pad size control\u003C/td>\n\u003Ctd>Mask controls outer dimension\u003C/td>\n\u003Ctd>Copper controls outer dimension\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Stencil release\u003C/td>\n\u003Ctd>Better — mask acts as wall\u003C/td>\n\u003Ctd>Relies on consistent paste volume\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Solder fillet shape\u003C/td>\n\u003Ctd>More barrel-shaped, less pad-side stress\u003C/td>\n\u003Ctd>Larger pad-side fillet, better stress relaxation\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Thermal cycling\u003C/td>\n\u003Ctd>Good\u003C/td>\n\u003Ctd>Better — NSMD pad edges absorb CTE mismatch\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Preferred for\u003C/td>\n\u003Ctd>≥ 0.5 mm pitch, coarse array\u003C/td>\n\u003Ctd>≤ 0.4 mm pitch, thermal-cycling-sensitive parts\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>APTPCB defaults to NSMD for BGA footprints. BGA packages are among the most thermally sensitive components on the board — the CTE mismatch between silicon die, package substrate, and PCB laminate creates repeated stress on the solder joints during power-on cycles and temperature changes. NSMD geometry gives a larger pad-side fillet and better thermal fatigue margin, which matters more at fine pitch where there is less compliance in the joint. When a package datasheet specifies SMD as mandatory, that requirement must be stated on the fabrication drawing.\u003C/p>\n\u003Ch2 id=\"bga-profile-vs-qfn-what-changes-for-reflow-soak-and-peak\" data-anchor-en=\"bga-profile-vs-qfn-what-changes-for-reflow-soak-and-peak\">BGA profile vs QFN: what changes for reflow, soak, and peak?\u003C/h2>\n\u003Cp>BGA soldering is reflow soldering. The steps are the same as for QFN, but the limits are tighter and the failure modes are different.\u003C/p>\n\u003Col>\n\u003Cli>Solder paste is printed onto the BGA pads through the stencil. For fine-pitch BGAs the stencil thickness and aperture size are chosen to give enough paste volume for a reliable joint without bridging.\u003C/li>\n\u003Cli>The placement machine sets the BGA on the paste, aligned by the package outline or by vision targeting on the ball pattern. APTPCB fine-pitch process holds ±25 µm placement accuracy.\u003C/li>\n\u003Cli>In the reflow oven the paste and balls melt together. Surface tension pulls the package toward the centroid of the pads — a small placement offset corrects itself at this stage.\u003C/li>\n\u003Cli>The joints solidify as the board cools.\u003C/li>\n\u003C/ol>\n\u003Cp>Two problems appear in BGA soldering that QFN rarely shows. The first is warpage: a large package and the board can both bow during heating, so some balls lose contact with the paste at peak temperature. That leaves a head-in-pillow defect, where the ball sits on the paste but does not merge with it. The second is voiding: gas trapped in the joint shows as round dark areas on X-ray. Both are controlled through stencil design, paste chemistry, moisture handling of packages and board, and the reflow profile.\u003C/p>\n\u003Cp>For the profile itself: a nitrogen atmosphere reduces oxidation and improves wetting, especially for lead-free SAC alloys. APTPCB targets a delta-T of 5 °C or less across the board during reflow. The soak zone matters for large packages — a steep ramp to peak can leave the center of a 40 mm FCBGA below the liquidus while the edges have already reflowed.\u003C/p>\n\u003Cp>For profile basics see the \u003Ca href=\"/en/blog/reflow-soldering-process\">reflow soldering process guide\u003C/a>. For board flatness during assembly see \u003Ca href=\"/en/blog/warpage-control-during-assembly\">warpage control during assembly\u003C/a>. For APTPCB's BGA and fine-pitch assembly capability, see \u003Ca href=\"/en/pcba/bga-qfn-fine-pitch\">BGA assembly services\u003C/a>.\u003C/p>\n\u003Ch2 id=\"x-ray-criteria-for-bga-which-defects-fail-ipc-a-610-and-which-you-can-rework\" data-anchor-en=\"x-ray-criteria-for-bga-which-defects-fail-ipc-a-610-and-which-you-can-rework\">X-ray criteria for BGA: which defects fail IPC-A-610 and which you can rework?\u003C/h2>\n\u003Cp>Most BGA guides explain that X-ray is needed and stop there. This one defines what the X-ray report must contain and which defects actually end a joint.\u003C/p>\n\u003Cp>AOI cameras can see whether a BGA is present and roughly aligned, but they cannot see the joints. X-ray inspection can. A 2D X-ray shows ball shape, bridging, missing balls, and voids from above. Angled or 3D X-ray helps separate overlapping features and identify head-in-pillow, which can look normal from straight above.\u003C/p>\n\u003Cp>The key defects and how they are classified:\u003C/p>\n\u003Cp>\u003Cstrong>Bridging\u003C/strong> between adjacent balls is a defect at any class level. It is not reworkable — the package must come off, the site must be cleaned, and a new package must be placed.\u003C/p>\n\u003Cp>\u003Cstrong>Missing balls\u003C/strong> are defects. If the ball was never placed, the joint has no mechanical or electrical connection. If the ball was lost after reflow, the cause must be investigated before the board is accepted.\u003C/p>\n\u003Cp>\u003Cstrong>Head-in-pillow (HiP)\u003C/strong> is a joint where the ball has softened and partially wet the pad but did not fully merge with the paste deposit. It can look like a good joint on 2D X-ray. Angled or 3D views are needed to identify it. HiP is a defect under IPC-A-610.\u003C/p>\n\u003Cp>\u003Cstrong>Voids\u003C/strong> are gas pockets in the joint. Small voids below the void acceptance limit in the purchase order are acceptable. The limit is typically set at 25 % of the joint cross-section area for BGAs, but this must be agreed before the build — IPC-A-610 gives guidance by class, not a single number. Void acceptance is one of the most common sources of dispute in BGA assembly and must be written into the order explicitly.\u003C/p>\n\u003Cp>What to put in the RFQ for inspection:\u003C/p>\n\u003Cul>\n\u003Cli>Which packages are subject to X-ray (typically all BGAs below 0.5 mm pitch and any package on an IPC-A-610 Class 3 board)\u003C/li>\n\u003Cli>Sampling plan: 100 % inspection, AQL level, or first article only\u003C/li>\n\u003Cli>Void acceptance limit by percentage of joint area\u003C/li>\n\u003Cli>Acceptance class: IPC-A-610 Class 2 or Class 3\u003C/li>\n\u003Cli>Whether angled views or 3D reconstruction are required\u003C/li>\n\u003Cli>Whether a void report is delivered with the lot\u003C/li>\n\u003C/ul>\n\u003Cp>The article on \u003Ca href=\"/en/blog/x-ray-criteria-for-bga-voiding-and-head-in-pillow\">X-ray criteria for BGA voiding and head-in-pillow\u003C/a> covers how to set those criteria, and the \u003Ca href=\"/en/pcba/xray-inspection\">PCB X-ray inspection\u003C/a> service covers sampling and reporting.\u003C/p>\n\u003Cp>Electrical test adds another layer. Boundary scan (JTAG) can check BGA connections that are otherwise unreachable, and functional test confirms the device works.\u003C/p>\n\u003Ch2 id=\"bga-package-types-which-one-matches-your-application\" data-anchor-en=\"bga-package-types-which-one-matches-your-application\">BGA package types: which one matches your application?\u003C/h2>\n\u003Cp>There are several BGA variants. These are the ones most likely to appear on a designer's BOM, with what each one demands from the board.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Package\u003C/th>\n\u003Cth>Construction\u003C/th>\n\u003Cth>Typical use\u003C/th>\n\u003Cth>Fan-out demand\u003C/th>\n\u003Cth>Inspection\u003C/th>\n\u003Cth>Rework difficulty\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>PBGA (plastic BGA)\u003C/td>\n\u003Ctd>Wire-bonded die on organic substrate, overmolded\u003C/td>\n\u003Ctd>Controllers, chipsets, general ICs\u003C/td>\n\u003Ctd>Moderate at coarser pitch; through vias often fit\u003C/td>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Moderate; package can be replaced or reballed\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>FCBGA (flip-chip BGA)\u003C/td>\n\u003Ctd>Die bumped and flipped onto a build-up substrate\u003C/td>\n\u003Ctd>CPUs, GPUs, FPGAs, network processors\u003C/td>\n\u003Ctd>High; large ball count, many layers, often HDI\u003C/td>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Hard; large body, warpage, high thermal mass\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>CBGA (ceramic BGA)\u003C/td>\n\u003Ctd>Ceramic substrate, often higher-melting balls\u003C/td>\n\u003Ctd>High-reliability and legacy parts\u003C/td>\n\u003Ctd>Moderate\u003C/td>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Hard; ceramic body and large thermal mass\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>CSP / fine-pitch BGA\u003C/td>\n\u003Ctd>Package body close to die size, small balls at fine pitch\u003C/td>\n\u003Ctd>Mobile, wearable, memory\u003C/td>\n\u003Ctd>High; usually microvias or via-in-pad\u003C/td>\n\u003Ctd>X-ray\u003C/td>\n\u003Ctd>Hard; small balls, very little margin\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>PoP (package on package)\u003C/td>\n\u003Ctd>Memory BGA stacked on a logic BGA\u003C/td>\n\u003Ctd>Mobile processors with stacked memory\u003C/td>\n\u003Ctd>High\u003C/td>\n\u003Ctd>X-ray, often at more than one angle\u003C/td>\n\u003Ctd>Hard; two levels of joints\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>LGA (land grid array)\u003C/td>\n\u003Ctd>Flat lands under the body, no balls\u003C/td>\n\u003Ctd>Modules, sensors, some power parts; CPUs in sockets\u003C/td>\n\u003Ctd>Moderate to high\u003C/td>\n\u003Ctd>X-ray for solder-down LGA\u003C/td>\n\u003Ctd>Moderate; low standoff makes cleaning harder\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>QFN (quad flat no-lead)\u003C/td>\n\u003Ctd>Perimeter pads plus a central thermal pad\u003C/td>\n\u003Ctd>Power, RF, small MCUs\u003C/td>\n\u003Ctd>Low; pads on the edge, thermal vias under the center\u003C/td>\n\u003Ctd>AOI for edges, X-ray for thermal pad\u003C/td>\n\u003Ctd>Moderate\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2 id=\"bga-rework-and-reballing-what-three-cycles-actually-means-on-the-line\" data-anchor-en=\"bga-rework-and-reballing-what-three-cycles-actually-means-on-the-line\">BGA rework and reballing: what three cycles actually means on the line\u003C/h2>\n\u003Cp>When a BGA joint is bad, the package has to come off the board. BGA rework uses a rework station that heats the part from above and the board from below under a controlled profile, lifts the package, cleans and re-tins the site, then places and reflows a new or prepared package.\u003C/p>\n\u003Cp>APTPCB's fine-pitch process limits rework to three cycles or fewer. Each cycle is another thermal excursion for the board and for nearby components — the board has already been through paste print, placement, and reflow before the first rework, and each additional cycle degrades the laminate, the plated barrel integrity of nearby vias, and the solder joints of adjacent components. The three-cycle limit is not a contractual ceiling; it is an engineering constraint that reflects the cumulative thermal damage to the board and the increased probability of latent defects.\u003C/p>\n\u003Cp>Reballing is a separate job. It prepares an off-board BGA package by removing the old solder balls and placing new ones, often to recover a valuable part or convert its alloy to match the board's paste. APTPCB's \u003Ca href=\"/en/pcba/bga-reballing\">BGA reballing service\u003C/a> separates reballing (the component) from board-level rework (the assembly). If you send packages for reballing, include the package drawing or ball map, ball diameter, alloy, pitch, moisture condition, and the inspection records you need.\u003C/p>\n\u003Ch2 id=\"what-to-specify-for-a-bga-board\" data-anchor-en=\"what-to-specify-for-a-bga-board\">What to specify for a BGA board\u003C/h2>\n\u003Cp>Put these in the fabrication and assembly package so both the board house and the assembler build what you designed:\u003C/p>\n\u003Cul>\n\u003Cli>BGA package drawing references: pitch, ball diameter, ball count, alloy\u003C/li>\n\u003Cli>PCB pad definition (solder-mask defined or not) and pad size for each BGA\u003C/li>\n\u003Cli>Fan-out structure: through vias, microvias, or via-in-pad, with fill and cap requirements\u003C/li>\n\u003Cli>Surface finish suited to fine-pitch soldering, and board thickness\u003C/li>\n\u003Cli>Stencil thickness or any step areas required under the BGA\u003C/li>\n\u003Cli>Moisture-sensitivity handling for the packages\u003C/li>\n\u003Cli>X-ray requirement: which parts, sampling level, and void acceptance limit\u003C/li>\n\u003Cli>Acceptance class (IPC-A-610 Class 2 or 3) and any rework limit\u003C/li>\n\u003Cli>Underfill or corner staking, if required\u003C/li>\n\u003C/ul>\n\u003Ch2 id=\"why-work-with-aptpcb-on-bga-boards\" data-anchor-en=\"why-work-with-aptpcb-on-bga-boards\">Why work with APTPCB on BGA boards?\u003C/h2>\n\u003Cp>APT reviews BGA footprints, fan-out, via-in-pad, and stencil design before release, and runs BGA builds with SPI, AOI, and X-ray on the same traveler. The \u003Ca href=\"/en/pcba/bga-qfn-fine-pitch\">BGA assembly team\u003C/a> supplies AOI, AXI, and void reports with the lot, and underfill, staking, and controlled rework are available when your program needs them. If the board itself is the hard part, the \u003Ca href=\"/en/pcb/hdi-pcb\">HDI PCB manufacturing\u003C/a> team can review whether the fan-out needs microvias or can stay on through vias.\u003C/p>\n\u003Cp>Relevant standards and references may include:\u003C/p>\n\u003Cul>\n\u003Cli>IPC-7095: design and assembly process implementation for BGAs\u003C/li>\n\u003Cli>IPC-7351: generic requirements for surface mount design and land pattern standard\u003C/li>\n\u003Cli>IPC-A-610: acceptability of electronic assemblies\u003C/li>\n\u003Cli>IPC J-STD-001: requirements for soldered electrical and electronic assemblies\u003C/li>\n\u003Cli>IPC/JEDEC J-STD-033: handling of moisture-sensitive devices\u003C/li>\n\u003C/ul>\n\u003C!-- faq:start -->\n\u003Ch2 id=\"frequently-asked-questions\" data-anchor-en=\"frequently-asked-questions\">Frequently asked questions\u003C/h2>\n\u003Ch3 id=\"what-is-a-bga-in-electronics\" data-anchor-en=\"what-is-a-bga-in-electronics\">What is a BGA in electronics?\u003C/h3>\n\u003Cp>A BGA (ball grid array) is a surface-mount IC package that uses a grid of solder balls under its body to connect to the PCB. It allows many connections in a small footprint and is common for processors, FPGAs, memory, and SoCs.\u003C/p>\n\u003Ch3 id=\"what-is-the-difference-between-bga-and-lga\" data-anchor-en=\"what-is-the-difference-between-bga-and-lga\">What is the difference between BGA and LGA?\u003C/h3>\n\u003Cp>A BGA has solder balls attached to its pads, and those balls form most of each joint. An LGA has flat lands with no balls, so the joint is made only from solder paste printed on the PCB, which gives a lower standoff height. LGAs are also used in sockets without solder.\u003C/p>\n\u003Ch3 id=\"how-are-bga-chips-soldered\" data-anchor-en=\"how-are-bga-chips-soldered\">How are BGA chips soldered?\u003C/h3>\n\u003Cp>BGA chips are soldered by reflow. Paste is printed on the PCB pads, the BGA is placed on the paste, and the board passes through a reflow oven where the balls and paste melt together and self-align. The joints are then checked by X-ray.\u003C/p>\n\u003Ch3 id=\"why-are-bga-joints-inspected-with-x-ray\" data-anchor-en=\"why-are-bga-joints-inspected-with-x-ray\">Why are BGA joints inspected with X-ray?\u003C/h3>\n\u003Cp>The joints are underneath the package, so cameras cannot see them. X-ray shows ball shape, bridges, missing balls, and voids. Angled or 3D X-ray helps detect head-in-pillow defects that can look normal in a straight-down view.\u003C/p>\n\u003Ch3 id=\"what-does-flip-chip-bga-mean\" data-anchor-en=\"what-does-flip-chip-bga-mean\">What does flip chip BGA mean?\u003C/h3>\n\u003Cp>In a flip chip BGA (FCBGA), the silicon die is turned face-down and bonded to the package substrate with small bumps instead of wire bonds. The substrate then carries the signals to the solder balls. The construction gives shorter connections and is common on CPUs, GPUs, and FPGAs.\u003C/p>\n\u003Ch3 id=\"can-a-bga-be-reworked-or-reused\" data-anchor-en=\"can-a-bga-be-reworked-or-reused\">Can a BGA be reworked or reused?\u003C/h3>\n\u003Cp>Yes. A rework station removes the BGA under a controlled heating profile, the board site is cleaned, and a new or reballed part is installed. Reballing replaces the solder balls on an off-board package so it can be placed again. Each rework cycle adds heat stress, so the number of cycles is usually limited.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Ch2 id=\"bga-pcb-and-assembly-quote-checklist\" data-anchor-en=\"bga-pcb-and-assembly-quote-checklist\">BGA PCB and assembly quote checklist\u003C/h2>\n\u003Cp>Use this when you request a BGA PCB and assembly quote from a board house.\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> BGA pitch: 0.3 / 0.4 / 0.5 / 0.65 / 0.8 / 1.0 mm (state which)\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Number of BGA packages and their board locations\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Fan-out structure: through-via, microvia, or via-in-pad\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Pad type: NSMD or SMD (state which per package)\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Inner layer copper weight: 1/2 oz (or state if different)\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Stackup: material, layer count, and finished thickness\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> HDI configuration: 1+N+1, 2+N+2, or other\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Laser drill size and tolerance: 0.075 mm ±tol\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Stacked microvia count and any IPC Class 3 stacked-via limit\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Assembly: SPI placement tolerance ±25 µm required Y/N\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> X-ray inspection coverage required Y/N\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Underfill specified Y/N, and which package(s)\u003C/li>\n\u003Cli>\u003Cinput disabled=\"\" type=\"checkbox\"> Rework cycles permitted and how many\u003C/li>\n\u003C/ul>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2 id=\"choosing-a-bga-with-the-board-in-mind\" data-anchor-en=\"choosing-a-bga-with-the-board-in-mind\">Choosing a BGA with the board in mind\u003C/h2>\n\u003Cp>The BGA you pick decides more than the schematic. Its ball pitch sets the via structure and layer count of the PCB, its size and warpage set how hard it is to solder, and its hidden joints decide how the build is inspected and repaired. Read the package drawing before you lock the part, compare it with a QFN or LGA option where one exists, and put the pitch, pad, fan-out, and X-ray requirements in the RFQ.\u003C/p>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/reflow-soldering-process\">reflow soldering process guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/warpage-control-during-assembly\">warpage control during assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/bga-qfn-fine-pitch\">BGA assembly services\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/x-ray-criteria-for-bga-voiding-and-head-in-pillow\">X-ray criteria for BGA voiding and head-in-pillow\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/xray-inspection\">PCB X-ray inspection\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcba/bga-reballing\">BGA reballing service\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb/hdi-pcb\">HDI PCB manufacturing\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,15,16,17,18,19,20],"What Is BGA","BGA Ball Grid Array","BGA Package","BGA Soldering","LGA vs BGA","BGA Balls","Flip Chip BGA","what-is-bga",{"blog":23,"breadcrumb":32,"faq":46},{"@context":24,"@type":25,"headline":4,"description":5,"image":8,"url":26,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":27,"articleSection":7,"author":28,"publisher":31},"https://schema.org","BlogPosting","https://aptpcb.com/en/blog/what-is-bga","What Is BGA, BGA Ball Grid Array, BGA Package, BGA Soldering, LGA vs BGA, BGA Balls, Flip Chip BGA",{"@type":29,"name":30},"Organization","APTPCB",{"@type":29,"name":30},{"@context":24,"@type":33,"itemListElement":34},"BreadcrumbList",[35,40,44],{"@type":36,"position":37,"name":38,"item":39},"ListItem",1,"Home","https://aptpcb.com/",{"@type":36,"position":41,"name":42,"item":43},2,"Blog","https://aptpcb.com/en/blog",{"@type":36,"position":45,"name":21,"item":26},3,{"@context":24,"@type":47,"mainEntity":48},"FAQPage",[49,55,59,63,67,71],{"@type":50,"name":51,"acceptedAnswer":52},"Question","What is a BGA in electronics?",{"@type":53,"text":54},"Answer","A BGA (ball grid array) is a surface-mount IC package that uses a grid of solder balls under its body to connect to the PCB. It allows many connections in a small footprint and is common for processors, FPGAs, memory, and SoCs.",{"@type":50,"name":56,"acceptedAnswer":57},"What is the difference between BGA and LGA?",{"@type":53,"text":58},"A BGA has solder balls attached to its pads, and those balls form most of each joint. An LGA has flat lands with no balls, so the joint is made only from solder paste printed on the PCB, which gives a lower standoff height. LGAs are also used in sockets without solder.",{"@type":50,"name":60,"acceptedAnswer":61},"How are BGA chips soldered?",{"@type":53,"text":62},"BGA chips are soldered by reflow. Paste is printed on the PCB pads, the BGA is placed on the paste, and the board passes through a reflow oven where the balls and paste melt together and self-align. The joints are then checked by X-ray.",{"@type":50,"name":64,"acceptedAnswer":65},"Why are BGA joints inspected with X-ray?",{"@type":53,"text":66},"The joints are underneath the package, so cameras cannot see them. X-ray shows ball shape, bridges, missing balls, and voids. Angled or 3D X-ray helps detect head-in-pillow defects that can look normal in a straight-down view.",{"@type":50,"name":68,"acceptedAnswer":69},"What does flip chip BGA mean?",{"@type":53,"text":70},"In a flip chip BGA (FCBGA), the silicon die is turned face-down and bonded to the package substrate with small bumps instead of wire bonds. The substrate then carries the signals to the solder balls. The construction gives shorter connections and is common on CPUs, GPUs, and FPGAs.",{"@type":50,"name":72,"acceptedAnswer":73},"Can a BGA be reworked or reused?",{"@type":53,"text":74},"Yes. A rework station removes the BGA under a controlled heating profile, the board site is cleaned, and a new or reballed part is installed. Reballing replaces the solder balls on an off-board package so it can be placed again. Each rework cycle adds heat stress, so the number of cycles is usually limited.",{"pcbManufacturingColumns":76,"capabilityColumns":201,"resourceColumns":232,"pcbaColumns":273},[77,125,154,183],{"heading":78,"links":79},"PCB Product Families",[80,83,86,89,92,95,98,101,104,107,110,113,116,119,122],{"label":81,"path":82},"FR-4 PCB","/pcb/fr4-pcb",{"label":84,"path":85},"High-Speed PCB","/pcb/high-speed-pcb",{"label":87,"path":88},"Multilayer PCB","/pcb/multilayer-pcb",{"label":90,"path":91},"HDI PCB","/pcb/hdi-pcb",{"label":93,"path":94},"Flexible PCB","/pcb/flex-pcb",{"label":96,"path":97},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":99,"path":100},"Ceramic PCB","/pcb/ceramic-pcb",{"label":102,"path":103},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":105,"path":106},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":108,"path":109},"Antenna PCB","/pcb/antenna-pcb",{"label":111,"path":112},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":114,"path":115},"Microwave PCB","/pcb/microwave-pcb",{"label":117,"path":118},"Metal Core PCB","/pcb/metal-core-pcb",{"label":120,"path":121},"High-Tg PCB","/pcb/high-tg-pcb",{"label":123,"path":124},"Backplane PCB","/pcb/backplane-pcb",{"sections":126},[127],{"heading":128,"links":129},"RF & Materials",[130,133,136,139,142,145,148,151],{"label":131,"path":132},"Rogers PCB","/materials/rf-rogers",{"label":134,"path":135},"Taconic PCB","/materials/taconic-pcb",{"label":137,"path":138},"Teflon PCB","/materials/teflon-pcb",{"label":140,"path":141},"Arlon PCB","/materials/arlon-pcb",{"label":143,"path":144},"Megtron PCB","/materials/megtron-pcb",{"label":146,"path":147},"ISOLA PCB","/materials/isola-pcb",{"label":149,"path":150},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":152,"path":153},"Impedance Control","/pcb/pcb-impedance-control",{"sections":155},[156],{"heading":157,"links":158},"Manufacturing / Stackups",[159,162,165,168,171,174,177,180],{"label":160,"path":161},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":163,"path":164},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":166,"path":167},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":169,"path":170},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":172,"path":173},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":175,"path":176},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":178,"path":179},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":181,"path":182},"Multi-Layer Laminated Structure","/pcb/multilayer-pcb-lamination-services",{"heading":184,"links":185},"Specialties & Resources",[186,189,192,195,198],{"label":187,"path":188},"PCB Surface Finishes (ENIG / ENEPIG / HASL / OSP / Immersion)","/pcb/pcb-surface-finishes",{"label":190,"path":191},"Drilling & Vias (Blind / Buried / Via-in-Pad / Backdrill / Half Hole)","/pcb/pcb-drilling",{"label":193,"path":194},"PCB Stackup (Standard / High-Layer / Flex / Rigid-Flex / Aluminum)","/pcb/pcb-stack-up",{"label":196,"path":197},"Profiles (Milling / V-Scoring / Depaneling)","/pcb/pcb-profiling",{"label":199,"path":200},"Quality & Inspection (AOI + X-Ray / Flying Probe / PCB DFM Check)","/pcb/pcb-quality",[202,207,212,217,222,227],{"links":203},[204],{"label":205,"path":206},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":208},[209],{"label":210,"path":211},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":213},[214],{"label":215,"path":216},"Flex PCB Capability","/capabilities/flex-pcb",{"links":218},[219],{"label":220,"path":221},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":223},[224],{"label":225,"path":226},"Metal PCB Capability","/capabilities/metal-pcb",{"links":228},[229],{"label":230,"path":231},"Ceramic PCB Capability","/capabilities/ceramic-pcb",[233,244,265],{"heading":234,"links":235},"Downloads",[236,239,242],{"label":237,"path":238},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":240,"path":241},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":181,"path":243},"/pcb/multi-layer-laminated-structure",{"heading":245,"links":246},"Tools",[247,250,253,256,259,262],{"label":248,"path":249},"Gerber Viewer","/tools/gerber-viewer",{"label":251,"path":252},"PCB Viewer","/tools/pcb-viewer",{"label":254,"path":255},"BOM Viewer","/tools/bom-viewer",{"label":257,"path":258},"3D Viewer","/tools/3d-viewer",{"label":260,"path":261},"Circuit Simulator","/tools/circuit-simulator",{"label":263,"path":264},"Impedance Calculator","/tools/impedance-calculator",{"heading":266,"links":267},"FAQ & Blog",[268,271],{"label":269,"path":270},"FAQ","/resources/faq",{"label":42,"path":272},"/blog",[274,304,328,361],{"heading":275,"links":276},"Core Services",[277,280,283,286,289,292,295,298,301],{"label":278,"path":279},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":281,"path":282},"NPI & Small Batch PCB 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Control","/pcba/incoming-quality-control",{"heading":362,"linkClass":363,"links":364},"Industry Applications (Entry)","text-nowrap",[365,368,371,374,377,380,383,386,389,392,395],{"label":366,"path":367},"Server / Data Center","/industries/server-data-center-pcb",{"label":369,"path":370},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":372,"path":373},"Medical","/industries/medical-pcb",{"label":375,"path":376},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":378,"path":379},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":381,"path":382},"Drone / UAV","/industries/drone-uav-pcb",{"label":384,"path":385},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":387,"path":388},"Power & New Energy","/industries/power-energy-pcb",{"label":390,"path":391},"Robotics & Automation","/industries/robotics-pcb",{"label":393,"path":394},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":396,"path":397},"PCB Industry Overview →","/pcb-industry-solutions",1791013421778]