[{"data":1,"prerenderedAt":966},["ShallowReactive",2],{"header-nav-en":3,"pcb-product-pcb-impedance-control-en":332,"resources-index":964},{"pcbManufacturingColumns":4,"capabilityColumns":129,"resourceColumns":160,"pcbaColumns":201},[5,53,82,111],{"heading":6,"links":7},"PCB Product Families",[8,11,14,17,20,23,26,29,32,35,38,41,44,47,50],{"label":9,"path":10},"FR-4 PCB","/pcb/fr4-pcb",{"label":12,"path":13},"High-Speed PCB","/pcb/high-speed-pcb",{"label":15,"path":16},"Multilayer PCB","/pcb/multilayer-pcb",{"label":18,"path":19},"HDI PCB","/pcb/hdi-pcb",{"label":21,"path":22},"Flexible PCB","/pcb/flex-pcb",{"label":24,"path":25},"Rigid Flex PCB","/pcb/rigid-flex-pcb",{"label":27,"path":28},"Ceramic PCB","/pcb/ceramic-pcb",{"label":30,"path":31},"Heavy Copper PCB","/pcb/heavy-copper-pcb",{"label":33,"path":34},"High Thermal PCB","/pcb/high-thermal-pcb",{"label":36,"path":37},"Antenna PCB","/pcb/antenna-pcb",{"label":39,"path":40},"High Frequency PCB","/pcb/high-frequency-pcb",{"label":42,"path":43},"Microwave PCB","/pcb/microwave-pcb",{"label":45,"path":46},"Metal Core PCB","/pcb/metal-core-pcb",{"label":48,"path":49},"High-Tg PCB","/pcb/high-tg-pcb",{"label":51,"path":52},"Backplane PCB","/pcb/backplane-pcb",{"sections":54},[55],{"heading":56,"links":57},"RF & Materials",[58,61,64,67,70,73,76,79],{"label":59,"path":60},"Rogers PCB","/materials/rf-rogers",{"label":62,"path":63},"Taconic PCB","/materials/taconic-pcb",{"label":65,"path":66},"Teflon PCB","/materials/teflon-pcb",{"label":68,"path":69},"Arlon PCB","/materials/arlon-pcb",{"label":71,"path":72},"Megtron PCB","/materials/megtron-pcb",{"label":74,"path":75},"ISOLA PCB","/materials/isola-pcb",{"label":77,"path":78},"Spread Glass FR-4","/materials/spread-glass-fr4",{"label":80,"path":81},"Impedance Control","/pcb/pcb-impedance-control",{"sections":83},[84],{"heading":85,"links":86},"Manufacturing / Stackups",[87,90,93,96,99,102,105,108],{"label":88,"path":89},"Quickturn Prototypes","/pcb/quick-turn-pcb",{"label":91,"path":92},"NPI & Small Batch (PCB)","/pcb/npi-small-batch-pcb-manufacturing",{"label":94,"path":95},"High-Volume Production","/pcb/mass-production-pcb-manufacturing",{"label":97,"path":98},"High Layer Count PCB","/pcb/high-layer-count-pcb",{"label":100,"path":101},"PCB Fabrication Process","/pcb/pcb-fabrication-process",{"label":103,"path":104},"Advanced PCB Manufacturing","/pcb/advanced-pcb-manufacturing",{"label":106,"path":107},"Special PCB Manufacturing","/pcb/special-pcb-manufacturing",{"label":109,"path":110},"Multi-Layer Laminated Structure","/pcb/multi-layer-laminated-structure",{"heading":112,"links":113},"Specialties & Resources",[114,117,120,123,126],{"label":115,"path":116},"PCB Surface Finishes (ENIG / ENEPIG / HASL / OSP / Immersion)","/pcb/pcb-surface-finishes",{"label":118,"path":119},"Drilling & Vias (Blind / Buried / Via-in-Pad / Backdrill / Half Hole)","/pcb/pcb-drilling",{"label":121,"path":122},"PCB Stackup (Standard / High-Layer / Flex / Rigid-Flex / Aluminum)","/pcb/pcb-stack-up",{"label":124,"path":125},"Profiles (Milling / V-Scoring / Depaneling)","/pcb/pcb-profiling",{"label":127,"path":128},"Quality & Inspection (AOI + X-Ray / Flying Probe / PCB DFM Check)","/pcb/pcb-quality",[130,135,140,145,150,155],{"links":131},[132],{"label":133,"path":134},"Rigid PCB Capability","/capabilities/rigid-pcb",{"links":136},[137],{"label":138,"path":139},"Rigid-Flex Capability","/capabilities/rigid-flex-pcb",{"links":141},[142],{"label":143,"path":144},"Flex PCB Capability","/capabilities/flex-pcb",{"links":146},[147],{"label":148,"path":149},"HDI PCB Capability","/capabilities/hdi-pcb",{"links":151},[152],{"label":153,"path":154},"Metal PCB Capability","/capabilities/metal-pcb",{"links":156},[157],{"label":158,"path":159},"Ceramic PCB Capability","/capabilities/ceramic-pcb",[161,171,192],{"heading":162,"links":163},"Downloads",[164,167,170],{"label":165,"path":166},"Materials Datasheet / Processing Notes","/resources/downloads-materials",{"label":168,"path":169},"PCB DFM Guidelines","/resources/dfm-guidelines",{"label":109,"path":110},{"heading":172,"links":173},"Tools",[174,177,180,183,186,189],{"label":175,"path":176},"Gerber Viewer","/tools/gerber-viewer",{"label":178,"path":179},"PCB Viewer","/tools/pcb-viewer",{"label":181,"path":182},"BOM Viewer","/tools/bom-viewer",{"label":184,"path":185},"3D Viewer","/tools/3d-viewer",{"label":187,"path":188},"Circuit Simulator","/tools/circuit-simulator",{"label":190,"path":191},"Impedance Calculator","/tools/impedance-calculator",{"heading":193,"links":194},"FAQ & Blog",[195,198],{"label":196,"path":197},"FAQ","/resources/faq",{"label":199,"path":200},"Blog","/blog",[202,232,262,295],{"heading":203,"links":204},"Core Services",[205,208,211,214,217,220,223,226,229],{"label":206,"path":207},"Turnkey PCB Assembly","/pcba/turnkey-assembly",{"label":209,"path":210},"NPI & Small Batch PCB Assembly","/pcba/npi-assembly",{"label":212,"path":213},"Mass Production PCB Assembly","/pcba/mass-production",{"label":215,"path":216},"Flex & Rigid-Flex PCB Assembly","/pcba/flex-rigid-flex",{"label":218,"path":219},"SMT & Through-Hole Assembly","/pcba/smt-tht",{"label":221,"path":222},"BGA PCB Assembly","/pcba/bga-qfn-fine-pitch",{"label":224,"path":225},"Components & BOM Management","/pcba/components-bom",{"label":227,"path":228},"Box Build Assembly","/pcba/box-build-assembly",{"label":230,"path":231},"PCB Assembly Testing & Quality","/pcba/testing-quality",{"heading":233,"links":234},"Supporting Services",[235,238,241,244,247,250,253,256,259],{"label":236,"path":237},"Every Support Touchpoint","/pcba/support-services",{"label":239,"path":240},"Stencil Lab","/pcba/pcb-stencil",{"label":242,"path":243},"Components Sourcing","/pcba/component-sourcing",{"label":245,"path":246},"IC Programming","/pcba/ic-programming",{"label":248,"path":249},"Conformal Coating","/pcba/pcb-conformal-coating",{"label":251,"path":252},"Selective Soldering","/pcba/pcb-selective-soldering",{"label":254,"path":255},"BGA Reballing","/pcba/bga-reballing",{"label":257,"path":258},"Cable Assembly","/pcba/cable-assembly",{"label":260,"path":261},"Wire Harness","/pcba/harness-assembly",{"heading":263,"links":264},"Quality & Testing",[265,268,271,274,277,280,283,286,289,292],{"label":266,"path":267},"Quality Inspection","/pcba/quality-system",{"label":269,"path":270},"First Article Inspection (FAI)","/pcba/first-article-inspection",{"label":272,"path":273},"Solder Paste Inspection (SPI)","/pcba/spi-inspection",{"label":275,"path":276},"AOI Optical Inspection","/pcba/aoi-inspection",{"label":278,"path":279},"X-Ray / CT Inspection","/pcba/xray-inspection",{"label":281,"path":282},"ICT In-Circuit Testing","/pcba/ict-test",{"label":284,"path":285},"Flying Probe Testing","/pcba/flying-probe-testing",{"label":287,"path":288},"FCT / Functional Testing","/pcba/fct-test",{"label":290,"path":291},"Final Inspection & Packing","/pcba/final-quality-inspection",{"label":293,"path":294},"Incoming Quality Control","/pcba/incoming-quality-control",{"heading":296,"linkClass":297,"links":298},"Industry Applications (Entry)","text-nowrap",[299,302,305,308,311,314,317,320,323,326,329],{"label":300,"path":301},"Server / Data Center","/industries/server-data-center-pcb",{"label":303,"path":304},"Automotive / EV","/industries/automotive-electronics-pcb",{"label":306,"path":307},"Medical","/industries/medical-pcb",{"label":309,"path":310},"Telecom / 5G","/industries/communication-equipment-pcb",{"label":312,"path":313},"Aerospace & Defense","/industries/aerospace-defense-pcb",{"label":315,"path":316},"Drone / UAV","/industries/drone-uav-pcb",{"label":318,"path":319},"Industrial Control & Automation","/industries/industrial-control-pcb",{"label":321,"path":322},"Power & New Energy","/industries/power-energy-pcb",{"label":324,"path":325},"Robotics & Automation","/industries/robotics-pcb",{"label":327,"path":328},"Security / Security Equipment","/industries/security-equipment-pcb",{"label":330,"path":331},"PCB Industry Overview →","/pcb-industry-solutions",{"seo":333,"hero":362,"trustBar":380,"sections":398,"testimonials":399,"faqs":400,"closingCta":366,"template":401,"layout":402,"modern":366,"newpageBody":403},{"title":334,"description":335,"canonical":336,"structuredData":337},"Controlled Impedance PCB Manufacturing | ±5Ω TDR-Verified | APTPCB","Controlled impedance PCB fabrication with ±5Ω / ±7% tolerance. Single-ended, differential, and coplanar structures simulated with 2D field solvers and 100% TDR-verified. 50Ω, 90Ω, 100Ω targets for USB, PCIe, DDR, HDMI, and Ethernet.","https://aptpcb.com/en/pcb/pcb-impedance-control",[338,348],{"@context":339,"@type":340,"name":341,"description":342,"provider":343,"url":336,"serviceType":341,"areaServed":347},"https://schema.org","Service","Controlled Impedance PCB Manufacturing","Controlled impedance PCB fabrication with ±5Ω / ±7% tolerance. Single-ended, differential, and coplanar structures simulated with 2D field solvers and 100% TDR-verified.",{"@type":344,"name":345,"url":346},"Organization","APTPCB","https://aptpcb.com","Worldwide",{"@context":339,"@type":349,"itemListElement":350},"BreadcrumbList",[351,356,360],{"@type":352,"position":353,"name":354,"item":355},"ListItem",1,"Home","https://aptpcb.com/en/",{"@type":352,"position":357,"name":358,"item":359},2,"PCB","https://aptpcb.com/en/pcb",{"@type":352,"position":361,"name":80,"item":336},3,{"title":363,"eyebrow":364,"description":365,"primaryCta":366,"secondaryCta":366,"image":367,"highlights":370},"Impedance Control PCB Manufacturing","Signal Integrity Engineering","From USB and HDMI routing on a compact IoT prototype to 112G PAM4 differential pairs on a 64-layer data center switch fabric, every high-speed design hinges on precise impedance control. APTPCB delivers impedance-controlled PCBs across all structure types, including single-ended, differential, and coplanar waveguide, with tolerances as tight as ±5Ω and 100% TDR verification on every production panel before shipment.",null,{"src":368,"alt":369},"/assets/img/pcb/pcb-stackup-stackup-pcb-hero.webp","Controlled impedance PCB manufacturing and signal integrity engineering",[371,374,377],{"value":372,"label":373},"± 5Ω / ± 7%","Impedance Tolerance",{"value":375,"label":376},"100% TDR","Every Panel Tested",{"value":378,"label":379},"Up to 64 L","Layer Range",[381,382,384,387,390,393,396,397],{"value":372,"label":373},{"value":375,"label":383},"Coupon Verification",{"value":385,"label":386},"50 / 75 / 90 / 100Ω","Standard Targets",{"value":388,"label":389},"2D Field Solver","Pre-Production Simulation",{"value":391,"label":392},"IPC-2141 / -2152","Design Standards",{"value":394,"label":395},"Up to 20 oz Cu","Heavy Copper Support",{"value":372,"label":373},{"value":375,"label":383},[],[],[],"newpage-longform","default",{"tint":404,"sections":405,"selector":778,"relatedServices":873,"geoReach":923,"finalCta":957,"useSiteFinalCta":644},"pcb",[406,418,465,532,564,579,633,645,694,723,743],{"id":407,"type":408,"theme":402,"eyebrow":409,"heading":410,"paragraphs":411,"image":414},"controlled-impedance-services","twoColIntro","Core Discipline","Controlled Impedance PCB Services for Global Engineering Teams",[412,413],"As a manufacturer trusted by signal integrity engineers across \u003Cstrong>North America, Europe, and the Asia-Pacific\u003C/strong>, APTPCB delivers production-grade controlled impedance on every board type, from standard 4-layer FR-4 to complex \u003Ca href=\"/en/pcb/pcb-stack-up\">64-layer hybrid stack-ups\u003C/a> mixing Rogers RF laminates with low-loss digital cores. Whether you are a hardware startup in \u003Cstrong>Silicon Valley\u003C/strong> routing USB4 on a compact wearable, or a telecom infrastructure team in \u003Cstrong>Stockholm\u003C/strong> designing 400G Ethernet switch fabrics with ±5Ω differential tolerance, our CAM engineers ensure your impedance targets are met from first prototype through volume production.","Our closed-loop impedance process covers the full workflow: we simulate every impedance structure using industry-standard 2D field-solver suites with frequency-dependent Dk/Df data from the actual laminate lot, compensate trace widths for factory-specific etch factors and copper profiles, place dedicated TDR test coupons on every production panel, and deliver a measured impedance report with each shipment. We support all mainstream laminates on the market — from standard FR-4 through ultra-low-loss \u003Ca href=\"/en/materials/megtron-pcb\">Megtron 6/7\u003C/a>, \u003Ca href=\"/en/materials/rf-rogers\">Rogers PTFE\u003C/a>, \u003Ca href=\"/en/materials/taconic-pcb\">Taconic\u003C/a>, and polyimide flex — and can source any specified material per your BOM requirements.",{"placeholder":415,"alt":416,"src":417},"[ Photograph: TDR oscilloscope screen showing clean impedance trace of a controlled impedance PCB test coupon ]","TDR oscilloscope verifying a controlled impedance PCB test coupon","/assets/img/pcb/pcb-impedance-control-tdr-test-coupon.webp",{"id":419,"type":420,"theme":421,"eyebrow":422,"heading":423,"description":424,"columns":425,"rows":430,"note":464},"impedance-types","splitTable","alt","Impedance Structures","Impedance Types We Manufacture","Every high-speed protocol specifies a particular impedance structure. We fabricate all standard and advanced configurations with full simulation support.",[426,427,428,429],"Structure Type","Description","Typical Targets","Common Protocols",[431,436,441,446,451,455,460],[432,433,434,435],"\u003Cstrong>Single-Ended Microstrip\u003C/strong>","One signal trace on an outer layer referenced to a ground plane directly below. The simplest and most common impedance structure.","50Ω, 75Ω","General I/O, clock signals, RF feeds, coaxial-to-PCB transitions",[437,438,439,440],"\u003Cstrong>Single-Ended Stripline\u003C/strong>","One signal trace sandwiched between two reference planes on inner layers. Provides better shielding and lower EMI than microstrip.","50Ω, 60Ω","Sensitive analog, inner-layer clocks, controlled-impedance bus lines",[442,443,444,445],"\u003Cstrong>Edge-Coupled Differential Microstrip\u003C/strong>","Two parallel traces on an outer layer, tightly coupled side by side. Coupling reduces crosstalk susceptibility and provides common-mode noise rejection.","90Ω, 100Ω","USB 2.0/3.x, HDMI, DisplayPort, LVDS, MIPI",[447,448,449,450],"\u003Cstrong>Edge-Coupled Differential Stripline\u003C/strong>","Two parallel traces between reference planes. Offers the tightest impedance uniformity and best EMI performance for high-speed differential pairs.","85Ω, 90Ω, 100Ω","PCIe Gen3/4/5/6, 10G/25G/100G Ethernet, DDR4/DDR5",[452,453,444,454],"\u003Cstrong>Broadside-Coupled Differential Stripline\u003C/strong>","Two traces stacked vertically on adjacent layers sharing reference planes. Saves routing space where horizontal coupling is not feasible.","Dense BGA breakout, high-channel-count backplanes",[456,457,458,459],"\u003Cstrong>Coplanar Waveguide (CPWG)\u003C/strong>","Signal trace flanked by coplanar ground on the same layer, with an additional ground plane below. Used in RF and mmWave designs for precise impedance control at high frequencies.","50Ω","5G mmWave, automotive radar (77 GHz), WLAN, GPS front-ends",[461,462,458,463],"\u003Cstrong>Coplanar Stripline\u003C/strong>","Coplanar waveguide buried between two reference planes. Combines coplanar shielding with stripline isolation for the best RF isolation in \u003Ca href=\"/en/pcb/high-frequency-pcb\">high-frequency PCB\u003C/a> designs.","Phased-array radar, satellite transponders, test & measurement","We also support asymmetric impedance structures, embedded resistor impedance matching, and custom target values outside standard ranges. \u003Ca href=\"/en/quote\">Contact our SI team\u003C/a> for non-standard requirements.",{"id":466,"type":420,"theme":402,"eyebrow":467,"heading":468,"description":469,"columns":470,"rows":476},"protocol-impedance-requirements","Design Reference","Protocol Impedance Requirements","Quick reference for impedance targets defined by common high-speed interface standards. These values must be met within the specified tolerance on the finished board.",[471,472,473,474,475],"Interface / Protocol","Impedance Type","Target (Ω)","Typical Tolerance","Notes",[477,483,488,492,496,501,506,510,513,517,520,524,527],[478,479,480,481,482],"\u003Cstrong>USB 2.0\u003C/strong>","Differential","90","± 10%","480 Mbps max; microstrip acceptable for most designs",[484,479,485,486,487],"\u003Cstrong>USB 3.x / USB4\u003C/strong>","85 – 90","± 8%","5 – 40 Gbps; tighter etch control needed; stripline preferred at 20 Gbps+",[489,479,490,481,491],"\u003Cstrong>PCIe Gen3 / Gen4\u003C/strong>","85 – 100","8 – 16 GT/s; requires \u003Ca href=\"/en/pcb/pcb-stack-up\">symmetric stack-up\u003C/a> for consistent Dk",[493,479,490,494,495],"\u003Cstrong>PCIe Gen5 / Gen6\u003C/strong>","± 5%","32 – 64 GT/s; spread-glass prepreg and ultra-low-loss laminates strongly recommended",[497,498,499,481,500],"\u003Cstrong>DDR4\u003C/strong>","Single-ended","40 – 60","Data lines typically 40Ω, clock/address 50Ω; JEDEC defined",[502,503,504,486,505],"\u003Cstrong>DDR5\u003C/strong>","Differential (clk) / SE (data)","40 / 50","Decision feedback equalization allows slightly more flexibility",[507,479,508,481,509],"\u003Cstrong>HDMI 2.1\u003C/strong>","100","48 Gbps; TMDS/FRL lanes; keep stub lengths under 100 mil",[511,479,508,486,512],"\u003Cstrong>10GBASE-KR Ethernet\u003C/strong>","Backplane Ethernet; \u003Ca href=\"/en/pcb/pcb-drilling\">back-drilling\u003C/a> recommended for stub removal",[514,479,515,494,516],"\u003Cstrong>100G / 400G Ethernet\u003C/strong>","92 – 100","PAM4 signaling; requires \u003Ca href=\"/en/materials/megtron-pcb\">Megtron 6/7\u003C/a> or equivalent ultra-low-loss material",[518,479,508,481,519],"\u003Cstrong>LVDS\u003C/strong>","Low-voltage differential signaling; common in display, camera, industrial I/O",[521,479,522,481,523],"\u003Cstrong>MIPI D-PHY / C-PHY\u003C/strong>","80 – 100","Mobile camera / display interface; short trace lengths typical",[525,479,490,481,526],"\u003Cstrong>SATA III\u003C/strong>","6 Gbps; relatively forgiving but impedance matching still critical at connector transitions",[528,529,530,494,531],"\u003Cstrong>50Ω RF (Coaxial Transition)\u003C/strong>","Single-ended / CPWG","50","SMA/U.FL launch; CPWG structure preferred; see \u003Ca href=\"/en/materials/rf-rogers\">Rogers RF laminates\u003C/a>",{"id":533,"type":534,"theme":535,"eyebrow":536,"heading":537,"description":538,"cards":539},"impedance-engineering-factors","processGrid","dark","Impedance Engineering","Factors That Determine PCB Impedance","Impedance is not a single variable — it is the result of multiple interacting physical parameters that must be controlled simultaneously during fabrication.",[540,544,548,552,556,560],{"number":541,"title":542,"copy":543},"01","Trace Width & Copper Thickness","Wider traces lower impedance; thicker copper (½ oz vs 1 oz vs 2 oz) also shifts the value. During etching, copper traces develop a trapezoidal cross-section rather than a perfect rectangle. Our CAM team compensates for this etch factor — typically 0.5 to 1.5 mil of width adjustment — using factory-calibrated correction tables for each copper weight.",{"number":545,"title":546,"copy":547},"02","Dielectric Thickness & Dk Value","The distance between trace and reference plane, combined with the dielectric constant (Dk) of the insulating material, is the most influential impedance factor. Different prepreg styles (1080, 2116, 7628) and resin systems (standard FR-4 Dk ≈ 4.2 – 4.5, \u003Ca href=\"/en/materials/megtron-pcb\">Megtron 6 Dk ≈ 3.71\u003C/a>, \u003Ca href=\"/en/materials/rf-rogers\">Rogers RO4350B Dk ≈ 3.48\u003C/a>) produce different impedance outcomes for the same trace geometry.",{"number":549,"title":550,"copy":551},"03","Differential Pair Spacing","For differential impedance, the gap between the two traces is critical. Tighter coupling (smaller gap) reduces differential impedance and improves common-mode rejection. We simulate the exact spacing using the chosen material's Dk at your operating frequency, then lock the gap dimension in our photoplot to prevent drift during imaging and etching.",{"number":553,"title":554,"copy":555},"04","Glass-Weave Effect & Dk Uniformity","Standard woven fiberglass creates a periodic Dk variation — traces over a glass bundle see higher Dk than traces over resin pockets. This causes intra-pair skew in differential pairs above 10 Gbps. We mitigate this by specifying \u003Ca href=\"/en/materials/spread-glass-fr4\">spread-glass fabrics\u003C/a> (1035, 1067, 1078 weaves) or by applying trace angle rotation in routing guidelines.",{"number":557,"title":558,"copy":559},"05","Solder Mask & Surface Finish","Solder mask applied over outer-layer microstrip traces adds a dielectric coating that lowers impedance by 1 – 3Ω compared to bare copper. The \u003Ca href=\"/en/pcb/pcb-surface-finishes\">surface finish\u003C/a> (ENIG, OSP, immersion tin, HASL) also affects the conductor surface roughness. We factor solder mask thickness and finish type into every outer-layer impedance simulation.",{"number":561,"title":562,"copy":563},"06","Temperature & Frequency Dependence","Material Dk varies with both temperature and frequency. A board simulated at 1 GHz using Dk = 4.2 may show different impedance when tested at 10 GHz where Dk may drop to 4.0. We use frequency-dependent Dk/Df data from laminate manufacturers — not just the generic \"@ 1 MHz\" catalog value — to ensure simulation accuracy at your actual operating frequency.",{"id":565,"type":566,"theme":402,"background":567,"layout":568,"eyebrow":569,"heading":570,"paragraphs":571,"image":575},"simulation-to-tdr-verification","twoColStory","warm","reverse","Closed-Loop Process","From Simulation to TDR Verification",[572,573,574],"Our impedance control workflow is a closed loop with no gaps. Before production begins, we build a precise cross-section model in our 2D field-solver suite — inputting the actual Dk/Df data from the laminate manufacturer's datasheet at your operating frequency, the specific prepreg style and resin content, the target copper weight, and the factory's measured etch factor for that copper thickness. The solver calculates the exact trace width and spacing needed to hit your impedance target.","After fabrication, we measure every production panel using Time-Domain Reflectometry (TDR). Dedicated test coupons — mirroring your board's actual trace geometry, layer, and dielectric — are placed on the panel margins. The TDR instrument sends a fast-rise pulse down the coupon and maps the impedance at every point. If the measured value falls outside your specified tolerance, the panel is rejected. The TDR report is included with every shipment.","For IPC Class 3 aerospace and medical builds, we also perform microsection analysis to physically verify dielectric thickness and copper profile under a metallurgical microscope, providing photographic evidence that the as-built \u003Ca href=\"/en/pcb/pcb-stack-up\">stack-up\u003C/a> matches the simulation model.",{"placeholder":576,"alt":577,"src":578},"[ Photograph: Dual-monitor workstation showing 2D field-solver cross-section model on left screen and TDR measurement waveform on right screen ]","Field-solver simulation and TDR verification workstation","/assets/img/pcb/pcb-impedance-control-field-solver-tdr-workstation.webp",{"id":580,"type":420,"theme":421,"eyebrow":581,"heading":582,"description":583,"columns":584,"rows":588},"impedance-control-specifications","Manufacturing Capability","Impedance Control Specifications","Our process controls and equipment enable repeatable impedance accuracy across the full range of board types and materials.",[585,586,587,475],"Parameter","Standard","Advanced",[589,594,599,604,608,613,618,623,628],[590,591,592,593],"\u003Cstrong>Impedance Tolerance\u003C/strong>","± 10% (single-ended > 50Ω)","± 5Ω (≤ 50Ω), ± 7% (> 50Ω)","Per APTPCB standard; applies to both single-ended and differential structures",[595,596,597,598],"\u003Cstrong>Supported Structures\u003C/strong>","Microstrip, Stripline","All types incl. CPWG, Broadside, Asymmetric","Coplanar waveguide structures require coplanar ground fill with controlled gap",[600,601,602,603],"\u003Cstrong>Minimum Trace Width\u003C/strong>","3.5 mil (89 µm)","2 mil (51 µm)","2/2 mil trace/space on both inner and outer layers; impedance-controlled traces at 2 mil require LDI imaging",[605,606,602,607],"\u003Cstrong>Minimum Diff. Pair Gap\u003C/strong>","4 mil (100 µm)","Tighter gaps need controlled etch compensation; \u003Ca href=\"/en/pcb/high-layer-count-pcb\">high-layer-count builds\u003C/a> may require wider gaps for registration",[609,610,611,612],"\u003Cstrong>Dk Range Supported\u003C/strong>","FR-4: 3.8 – 4.6","PTFE/Rogers: 2.2 – 10.2","All mainstream laminates supported per customer BOM — standard FR-4, high-Tg, low-loss, ultra-low-loss, PTFE, ceramic-filled, polyimide, and any commercially available material can be sourced to match your requirements",[614,615,616,617],"\u003Cstrong>TDR Equipment Rise Time\u003C/strong>","200 ps","35 ps","35 ps rise time resolves impedance discontinuities as small as 2 mm along the trace",[619,620,621,622],"\u003Cstrong>Coupon Types\u003C/strong>","Panel-edge coupons","Embedded in-board coupons","In-board coupons available for military/aerospace programs requiring per-board traceability",[624,625,626,627],"\u003Cstrong>Frequency-Dependent Simulation\u003C/strong>","Up to 6 GHz","Up to 70 GHz","For mmWave applications; uses manufacturer-measured Dk/Df at actual frequency band",[629,630,631,632],"\u003Cstrong>Copper Roughness Modeling\u003C/strong>","Standard foil (RTF)","HVLP / VLP / Profile-free","Surface roughness adds 5 – 15% insertion loss at frequencies above 10 GHz; \u003Ca href=\"/en/pcb/pcb-surface-finishes\">surface finish selection\u003C/a> impacts this",{"id":634,"type":635,"title":636,"description":637,"primary":638,"secondary":641,"showInNav":644},"impedance-mid-cta","ctaBlock","Need Impedance Control on Your Next Board?","Upload your Gerber files or stack-up drawing — our CAM team will provide a detailed impedance simulation report and DFM review within one business day.",{"label":639,"href":640},"Upload for Impedance Review","/quote",{"label":642,"href":643},"Talk to SI Engineer","/contact",false,{"id":646,"type":420,"theme":402,"eyebrow":647,"heading":648,"description":649,"columns":650,"rows":656,"note":693},"laminate-dk-df-reference","Material Properties","Laminate Dk & Df Quick Reference","The dielectric constant (Dk) and dissipation factor (Df) of your chosen laminate directly determine trace impedance and signal loss. We maintain inventory and pressing recipes for all major material systems.",[651,652,653,654,655],"Material Family","Representative Grades","Dk (@ 10 GHz)","Df (@ 10 GHz)","Best For",[657,663,669,675,681,687],[658,659,660,661,662],"\u003Cstrong>Standard FR-4\u003C/strong>","Shengyi S1000-2, ITEQ IT-180A, Nan Ya NPG-170, Ventec VT-47, KB-6167F","4.2 – 4.5","0.018 – 0.025","General digital up to ~3 Gbps; cost-sensitive designs",[664,665,666,667,668],"\u003Cstrong>Mid-Loss FR-4\u003C/strong>","Isola 370HR, Shengyi S1000-2ME, ITEQ IT-958G, Ventec VT-481","3.9 – 4.2","0.010 – 0.015","10G Ethernet, PCIe Gen3/4, DDR4/DDR5",[670,671,672,673,674],"\u003Cstrong>Low-Loss\u003C/strong>","\u003Ca href=\"/en/materials/megtron-pcb\">Megtron 4 (R-5775K)\u003C/a>, Isola I-Tera MT40, ITEQ IT-968, Nelco N7000-2 HT","3.6 – 3.9","0.005 – 0.009","25G/50G SerDes, PCIe Gen5, high-speed backplanes",[676,677,678,679,680],"\u003Cstrong>Ultra-Low-Loss\u003C/strong>","Megtron 6 (R-5775G), Megtron 7, Isola I-Speed, Tachyon 100G, Shengyi S7439G","3.4 – 3.7","0.002 – 0.005","100G/400G data center, PCIe Gen6, 56G/112G PAM4",[682,683,684,685,686],"\u003Cstrong>PTFE / Ceramic-Filled\u003C/strong>","\u003Ca href=\"/en/materials/rf-rogers\">Rogers RO4350B\u003C/a>, RO4835, RO3003, RT/duroid 5880, \u003Ca href=\"/en/materials/taconic-pcb\">Taconic RF-35\u003C/a>, TLY, \u003Ca href=\"/en/materials/arlon-pcb\">Arlon AD255\u003C/a>, DiClad 880","2.2 – 3.66","0.001 – 0.004","Automotive radar, 5G mmWave, satellite, RF front-ends",[688,689,690,691,692],"\u003Cstrong>Polyimide (Flex)\u003C/strong>","DuPont Pyralux AP/LF/HT, Panasonic Felios R-F775, Shengyi SF305C, Taiflex, Doosan","3.2 – 3.5","0.005 – 0.010","\u003Ca href=\"/en/pcb/rigid-flex-pcb\">Rigid-flex\u003C/a> impedance-controlled flex tails; dynamic bending applications","Dk/Df values are approximate at 10 GHz per manufacturer datasheets. Actual values vary with resin content, glass style, and measurement method. The materials listed above are representative examples — APTPCB supports all mainstream rigid and flex laminates on the market and can source any commercially available material per your BOM. Our simulation uses the exact laminate lot data provided by the material supplier.",{"id":695,"type":696,"theme":567,"eyebrow":697,"heading":698,"cards":699},"industry-applications","applicationsGrid","Applications","Industries Requiring Controlled Impedance",[700,704,708,711,715,719],{"eyebrow":701,"title":702,"copy":703},"Networking & Data Centers","100G/400G Switch & Server Boards","PAM4 signaling at 56G/112G per lane demands tight differential impedance on ultra-low-loss laminates with HVLP copper and \u003Ca href=\"/en/pcb/pcb-drilling\">back-drilled via stubs\u003C/a>.",{"eyebrow":705,"title":706,"copy":707},"Automotive","ADAS Radar & EV Power Electronics","77 GHz radar modules require CPWG structures on Rogers or Taconic PTFE with tight impedance tolerance. EV battery management systems need impedance-matched CAN/LIN buses on \u003Ca href=\"/en/pcb/heavy-copper-pcb\">heavy copper boards up to 20 oz\u003C/a>.",{"eyebrow":312,"title":709,"copy":710},"Avionics & Phased-Array Radar","MIL-PRF-31032 and IPC-6012DS Class 3/A boards with per-coupon TDR traceability, microsection verification, and the tightest impedance tolerance on \u003Ca href=\"/en/materials/arlon-pcb\">polyimide or high-Tg hybrid\u003C/a> stack-ups.",{"eyebrow":712,"title":713,"copy":714},"Medical Devices","Imaging & Diagnostic Equipment","Ultrasound transducer boards and CT/MRI data acquisition systems with differential impedance control on noise-sensitive analog channels. IPC Class 3 reliability with full impedance documentation.",{"eyebrow":716,"title":717,"copy":718},"Telecom & 5G","Base Station & Small Cell RRUs","Hybrid stack-ups mixing RF front-end layers on Rogers with digital baseband on low-loss FR-4. CPWG and microstrip impedance must be consistent from DC to 40+ GHz across operating temperature range.",{"eyebrow":720,"title":721,"copy":722},"Consumer & IoT","Smartphones, Wearables & SSD Controllers","Compact \u003Ca href=\"/en/pcb/hdi-pcb\">HDI boards\u003C/a> with fine-pitch BGA breakout requiring impedance-controlled microvias and stripline pairs on ultra-thin dielectrics down to 2 mil.",{"id":724,"type":725,"theme":421,"eyebrow":726,"heading":727,"blocks":728},"impedance-control-design-guidelines","proseSection","Design Best Practices","Impedance Control Design Guidelines",[729,731,734,737,740],{"copy":730},"Successful impedance control starts at the schematic and layout stage — long before the board reaches the factory. Engineers should define impedance targets for each signal class in their constraint manager and communicate these requirements clearly on the fabrication drawing. A well-documented impedance table listing the layer, structure type, target value, tolerance, and trace width/spacing intent prevents ambiguity and reduces DFM iterations.",{"heading":732,"copy":733},"Trace Routing Practices","Maintain consistent trace width along the entire impedance-controlled net. Avoid necking down differential pairs at via transitions unless absolutely necessary, and when you must, keep the necked region as short as possible (ideally under 50 mil). Route differential pairs with matched length within ±5 mil per pair, and maintain at least 3× the trace width as clearance from adjacent signals to minimize crosstalk coupling.",{"heading":735,"copy":736},"Reference Plane Integrity","Every impedance-controlled trace needs a continuous, unbroken reference plane directly adjacent. Splits, slots, or excessive via anti-pads in the reference plane create impedance discontinuities that no amount of trace-width tuning can fix. When a signal must cross a plane split, bridge it with stitching capacitors and accept that impedance will be degraded in that region. For \u003Ca href=\"/en/pcb/pcb-stack-up\">multilayer stack-ups\u003C/a>, dedicate full planes to ground rather than splitting power and ground on the same layer.",{"heading":738,"copy":739},"Via Transitions","Through-hole vias introduce a capacitive discontinuity in impedance-controlled paths. For signals above 10 Gbps, use back-drilled vias or blind/buried microvias to eliminate the via stub. Place ground vias adjacent to signal vias (within 10 mil) to maintain the return-current path. In differential pairs, keep via-to-via spacing identical to the trace-to-trace spacing to preserve the differential impedance through the transition.",{"heading":741,"copy":742},"Documentation for Your Fabricator","Include a clear impedance control table on your fab drawing specifying: layer number, structure type (microstrip/stripline/CPWG), single-ended or differential, target impedance in Ohms, tolerance (±5/8/10%), and reference layer. Also note any layers where solder mask should be opened over impedance traces. This documentation enables our CAM team to run accurate simulations and propose trace-width adjustments before production — reducing your time to first-article approval.",{"id":744,"type":745,"theme":402,"eyebrow":196,"heading":746,"items":747},"impedance-faq","faqList","Controlled Impedance PCB FAQ",[748,751,754,757,760,763,766,769,772,775],{"question":749,"answer":750},"What impedance tolerance does APTPCB offer?","Our standard controlled impedance tolerance is \u003Cstrong>±5Ω for targets at or below 50Ω\u003C/strong> and \u003Cstrong>±7% for targets above 50Ω\u003C/strong>. For a 100Ω differential target, ±7% means the measured value must fall between 93Ω and 107Ω. This tolerance applies to both single-ended and differential structures. Every production panel is verified with TDR test coupons, and the measured impedance report is included with shipment. For projects requiring tighter tolerance, please contact our SI engineering team to discuss material and process options.",{"question":752,"answer":753},"What is a TDR test coupon and where is it placed?","A TDR coupon is a dedicated test structure — matching the exact trace width, spacing, layer, and dielectric of your impedance-controlled nets — placed on the production panel margins outside the individual board outlines. After fabrication, we probe these coupons with a TDR instrument to measure the actual impedance. The coupons are sacrificed during depaneling and do not appear on your finished boards. For military or aerospace programs, we can also place coupons within the board outline for per-unit traceability.",{"question":755,"answer":756},"How does solder mask affect outer-layer impedance?","Solder mask (typically Dk ≈ 3.3 – 4.0, thickness 0.5 – 1.0 mil) acts as an additional dielectric layer over microstrip traces. This reduces impedance by 1 – 3Ω compared to bare copper. We always include solder mask in our outer-layer impedance simulation. If your design requires very tight tolerance on outer-layer impedance, we can selectively open the solder mask over critical traces (impedance trace windows).",{"question":758,"answer":759},"Can you control impedance on flex and rigid-flex boards?","Yes. Polyimide flex layers have a Dk of approximately 3.2 – 3.5, which is lower than FR-4. We simulate impedance on flex layers using the specific polyimide Dk and adhesive thickness. For \u003Ca href=\"/en/pcb/rigid-flex-pcb\">rigid-flex boards\u003C/a>, the impedance target may differ between the rigid sections (FR-4 dielectric) and the flex sections (polyimide dielectric). We provide separate impedance models for each zone and adjust trace widths accordingly.",{"question":761,"answer":762},"Why did your CAM team change my trace width?","During chemical etching, the copper trace develops a trapezoidal cross-section (wider at the base, narrower at the top). Additionally, prepreg resin flow during pressing can shift the actual dielectric thickness slightly from the nominal value. Our CAM engineers adjust your drawn trace width — typically by 0.5 to 1.5 mil — to compensate for these factory-specific variables and ensure the final physical trace hits the impedance target. We always submit these adjustments for your review and approval before production.",{"question":764,"answer":765},"What is the difference between microstrip and stripline impedance?","Microstrip traces are on outer layers with one reference plane below and solder mask (or air) above — they have lower shielding and slightly higher impedance for the same trace width. Stripline traces are buried between two reference planes on inner layers — they offer better shielding, tighter impedance uniformity, and lower EMI, but require wider traces to achieve the same impedance value because they are fully surrounded by dielectric material. High-speed differential signals (PCIe Gen5+, 100G Ethernet) are typically routed as edge-coupled differential stripline for best performance.",{"question":767,"answer":768},"What is coplanar waveguide (CPWG) and when should I use it?","CPWG is an impedance structure where the signal trace is flanked by ground copper on the same layer, with a ground plane underneath. The coplanar ground provides additional shielding and allows impedance tuning through the trace-to-ground gap. CPWG is the preferred structure for RF and mmWave designs (5G, 77 GHz radar, WLAN) because it provides excellent impedance control at high frequencies and clean transitions to coaxial connectors (SMA, U.FL, SMPM).",{"question":770,"answer":771},"Do you support impedance control on aluminum or metal-core PCBs?","Yes, but with limitations. \u003Ca href=\"/en/pcb/aluminum-pcb\">Metal-core PCBs\u003C/a> typically have only 1 – 2 signal layers with a thick dielectric (75 – 200 µm) over the metal base. We can control single-ended microstrip impedance on these boards, but differential pairs and stripline structures require multilayer construction. For LED driver or power designs that need both thermal management and impedance control, we recommend a hybrid approach with selective copper-coin thermal vias in a standard FR-4 multilayer stack.",{"question":773,"answer":774},"How does copper roughness affect impedance at high frequencies?","Standard electrodeposited (STD/RTF) copper has a surface roughness of 5 – 10 µm, which causes the effective signal path length to increase at higher frequencies as current flows along the rough surface contour. This adds 5 – 15% insertion loss above 10 GHz and can slightly shift impedance. For 25G+ signals, we recommend HVLP (Hyper Very Low Profile, ~2 µm roughness) or VLP copper foil and include the Hammerstad-Jensen or Huray roughness model in our impedance simulation.",{"question":776,"answer":777},"Can you control impedance on a hybrid Rogers/FR-4 stack-up?","Absolutely — this is one of our specialties. In a hybrid \u003Ca href=\"/en/pcb/pcb-stack-up\">stack-up\u003C/a>, the RF signal layer on \u003Ca href=\"/en/materials/rf-rogers\">Rogers\u003C/a> (e.g., RO4350B, Dk ≈ 3.48) will have a different trace width requirement than the digital signal layers on FR-4 (Dk ≈ 4.2). We simulate each layer independently using the correct material Dk and provide a combined impedance report. The key challenge is bonding dissimilar materials with compatible prepregs to prevent CTE mismatch delamination during SMT reflow.",{"id":779,"eyebrow":780,"heading":781,"description":782,"title":783,"label":426,"placeholder":784,"defaultText":785,"quoteBaseUrl":640,"quoteMode":786,"groups":787},"selector","Interactive Tool","Impedance Structure Selector","Select an impedance structure type to see the typical cross-section geometry, key parameters, and design considerations.","Select Impedance Structure","-- Select --","Select a structure to view impedance engineering details.","plain",[788],{"label":789,"options":790},"Structure Types",[791,808,821,834,847,860],{"value":792,"label":793,"rows":794,"quoteLabel":807},"se-ms","Single-Ended Microstrip",[795,799,803],[796],{"label":797,"value":798},"Geometry","Outer-layer trace over one ground plane",[800],{"label":801,"value":802},"Key Parameters","Trace width, dielectric height, copper thickness, solder mask",[804],{"label":805,"value":806},"Design Tip","Solder mask can reduce impedance by about 1 to 3Ω, so include mask openings or mask thickness in simulation","Request Impedance Review →",{"value":809,"label":810,"rows":811,"quoteLabel":807},"se-sl","Single-Ended Stripline",[812,815,818],[813],{"label":797,"value":814},"Inner-layer trace between two reference planes",[816],{"label":801,"value":817},"Trace width, upper and lower dielectric spacing, copper thickness",[819],{"label":805,"value":820},"Symmetric stripline is preferred; asymmetric offset stripline must be simulated separately",{"value":822,"label":823,"rows":824,"quoteLabel":807},"df-ms","Differential Microstrip",[825,828,831],[826],{"label":797,"value":827},"Two parallel outer-layer traces referenced to a common plane",[829],{"label":801,"value":830},"Trace width, pair gap, dielectric height, copper thickness",[832],{"label":805,"value":833},"Keep pair gap constant through the full route; BGA fan-out gap changes create discontinuities",{"value":835,"label":836,"rows":837,"quoteLabel":807},"df-sl","Differential Stripline",[838,841,844],[839],{"label":797,"value":840},"Two coupled traces between two reference planes",[842],{"label":801,"value":843},"Trace width, pair gap, upper and lower dielectric spacing",[845],{"label":805,"value":846},"Preferred for PCIe Gen5+ and 100G+ Ethernet; use spread-glass prepreg to minimize skew",{"value":848,"label":849,"rows":850,"quoteLabel":807},"cpwg","Coplanar Waveguide (CPWG)",[851,854,857],[852],{"label":797,"value":853},"Center trace flanked by coplanar ground with a ground plane below",[855],{"label":801,"value":856},"Trace width, coplanar gap, dielectric height",[858],{"label":805,"value":859},"Via-stitch the coplanar ground to the lower plane at small spacing to prevent slot-line mode",{"value":861,"label":862,"rows":863,"quoteLabel":807},"brd","Broadside-Coupled Stripline",[864,867,870],[865],{"label":797,"value":866},"Two vertically stacked traces on adjacent inner layers",[868],{"label":801,"value":869},"Trace width, vertical separation, plane spacing",[871],{"label":805,"value":872},"Saves horizontal space for dense BGA breakouts but requires precise layer-to-layer registration",{"eyebrow":874,"heading":875,"description":876,"categories":877},"Explore Further","Related PCB Services & Materials","Controlled impedance connects to every aspect of PCB design — from stack-up architecture to material selection to via drilling.",[878,893,908],{"label":879,"links":880},"Stack-Up & Materials",[881,884,887,890],{"label":882,"href":122,"icon":883},"PCB Stack-Up Design & Manufacturing","📐",{"label":885,"href":72,"icon":886},"Panasonic Megtron 4/6/7 Laminates","💡",{"label":888,"href":60,"icon":889},"Rogers RO4350B / RO3003","📡",{"label":891,"href":78,"icon":892},"Spread-Glass FR-4 PCB","🔩",{"label":894,"links":895},"Fabrication Services",[896,899,902,905],{"label":897,"href":119,"icon":898},"PCB Drilling & Back-Drilling","⚙️",{"label":900,"href":98,"icon":901},"High-Layer-Count PCB (20 - 64L)","📊",{"label":903,"href":19,"icon":904},"HDI PCB Manufacturing","🔬",{"label":906,"href":40,"icon":907},"High-Frequency PCB","📶",{"label":909,"links":910},"Testing & Quality",[911,914,917,920],{"label":912,"href":128,"icon":913},"PCB Quality Assurance","🛡️",{"label":915,"href":116,"icon":916},"Surface Finishes (ENIG, OSP, HASL)","✨",{"label":918,"href":89,"icon":919},"Quick-Turn Prototyping","⏱️",{"label":921,"href":207,"icon":922},"Turnkey PCB Assembly (PCBA)","🏭",{"eyebrow":924,"heading":925,"description":926,"cards":927},"Global Engineering Reach","Controlled Impedance PCB Services for Engineers Worldwide","Signal integrity engineers across telecom, automotive, aerospace, and data center industries worldwide rely on APTPCB for precision impedance control with full TDR verification and same-day DFM review.",[928,936,942,950],{"region":929,"name":930,"copy":931,"tags":932},"North America","USA · Canada · Mexico","Data center OEMs in Silicon Valley, defense primes in the Washington D.C. corridor, and automotive Tier-1 suppliers in Michigan rely on our TDR-verified impedance-controlled boards for 100G+ switch fabrics and ADAS radar modules.",[933,934,935],"Data Center","Defense","ADAS Radar",{"region":937,"name":938,"copy":939,"tags":940},"Europe","Germany · UK · Sweden · France","Automotive radar suppliers in Stuttgart, telecom infrastructure teams in Stockholm, and medical imaging innovators in the UK source our impedance-controlled boards with hybrid Rogers/FR-4 stack-ups.",[705,941,306],"5G Telecom",{"region":943,"name":944,"copy":945,"tags":946},"Asia-Pacific","Japan · South Korea · Taiwan · India","Semiconductor companies and server OEMs across APAC utilize our impedance simulation and TDR verification services for high-speed SerDes validation before volume production release.",[947,948,949],"Semiconductor","Server OEM","SerDes",{"region":951,"name":952,"copy":953,"tags":954},"Israel & Middle East","Israel · UAE · Saudi Arabia","Defense electronics and satellite communication programs in the region rely on our CPWG impedance control on PTFE laminates with full microsection documentation and MIL-spec traceability.",[955,934,956],"Satellite","CPWG",{"heading":958,"description":959,"primary":960,"secondary":962},"Get Your Impedance Simulation Report","Share your Gerber data, impedance targets, and material preference. Our CAM team will return a detailed impedance simulation report, trace-width adjustment recommendations, and quotation within one business day.",{"label":961,"href":640},"Upload for Impedance Quote",{"label":963,"href":640},"Full Quote Page ->",{"downloads":965},[],1776310231748]