Cleaning and Surface Preparation

cleaning and surface preparation: what this playbook covers (and who it’s for)

This guide is designed for hardware engineers, quality managers, and procurement leads who need to ensure the reliability of their printed circuit boards (PCBs) and assemblies (PCBAs). While often overlooked, cleaning and surface preparation is the invisible foundation of electronic reliability. It is not merely about aesthetics; it is about ensuring chemical bonding, electrical isolation, and thermal transfer. Without proper surface energy and contaminant removal, even the most expensive materials will fail.

In this playbook, we move beyond generic advice to specific engineering requirements. You will find actionable specifications for ionic contamination limits, surface roughness targets for adhesion, and validation protocols for critical interfaces. We address high-stakes applications, such as die attach on ceramic substrates and high-power LED MCPCB assembly and reflow, where surface conditions directly dictate product lifespan.

At APTPCB (APTPCB PCB Factory), we see firsthand how poor surface prep leads to field failures like delamination and electrochemical migration. This guide helps you define the right specs upfront, identify risks in your supply chain, and validate that your manufacturer is executing the process correctly. It provides the tools to move from "hoping it's clean" to "proving it's compliant."

When cleaning and surface preparation is the right approach (and when it isn’t)

Effective cleaning protocols must be matched to the complexity of the board and the harshness of the operating environment; over-specifying adds cost, while under-specifying invites failure.

When rigorous cleaning and surface preparation is mandatory:

High-Reliability Sectors: Aerospace, automotive, and medical devices where IPC Class 3 standards apply. Any ionic residue here can cause dendritic growth under humid conditions.
Advanced Assembly Processes: Applications involving wire bonding or die attach on ceramic substrates. These interfaces require pristine surfaces (often plasma-treated) to achieve acceptable shear strength.
Conformal Coating & Potting: If you plan to apply coating, the surface energy must be high enough (>38-40 dynes/cm) to prevent de-wetting or peeling.
High-Power Thermal Management: For LED MCPCB assembly and reflow, the interface between the thermal pad and the heatsink must be free of oxidation and oils to ensure maximum heat transfer.
Fine Pitch Technology: When using 0201 components or fine-pitch BGAs, flux residues can easily bridge gaps if not thoroughly removed.

When standard/minimal cleaning is acceptable:

Consumer Toys/Gadgets: Short-lifespan products operating in controlled, dry environments often rely on "no-clean" flux processes without additional washing.
Prototyping for Fit Checks: If the board is only for mechanical verification and will not be powered or stressed, standard cosmetic cleaning is sufficient.
Cost-Critical Disposable Electronics: Where the cost of washing (equipment, water, energy) exceeds the cost of a potential failure.

Specs & requirements (before quoting)

To ensure your manufacturer understands your expectations, you must translate "clean" into measurable data points in your fabrication notes.

Ionic Contamination Limit: Specify a maximum limit, typically < 1.56 µg/cm² NaCl equivalent (per IPC-6012/J-STD-001), or tighter (< 0.75 µg/cm²) for high-voltage applications.
Surface Energy (Dyne Level): For boards receiving conformal coating or underfill, require a surface energy test result of > 40 dynes/cm to ensure proper wetting.
Micro-etch Depth: For multilayer bonding or solder mask application, specify a copper micro-etch depth (e.g., 20–40 micro-inches) to create the necessary mechanical anchor profile.
Oxide Removal: Explicitly state that copper pads must be free of oxidation prior to surface finish application (ENIG, HASL, OSP) to prevent "black pad" or non-wetting.
Flux Residue Class: If using No-Clean flux, specify "Low Residue" or "Clear Residue." If using Water-Soluble flux, mandate 100% wash with deionized (DI) water.
Plasma Treatment: For die attach on ceramic substrates or PTFE/Teflon laminates, require plasma cleaning (Argon/Oxygen mix) to activate the surface before bonding.
Water Quality: Mandate the use of DI water with resistivity > 10 MΩ·cm for final rinse stages to prevent re-deposition of minerals.
Drying Protocol: Define baking requirements (e.g., 120°C for 2 hours) post-cleaning to eliminate trapped moisture, especially for hygroscopic materials like polyimide.
Solderability Standard: Reference J-STD-003 for PCB solderability. The surface prep must ensure > 95% wetting coverage.
Visual Cleanliness: Specify inspection at 10x-40x magnification per IPC-A-610 to reject visible residues, white haze, or particulate matter.
Handling Protocols: Require operators to use powder-free gloves and edge-handling protocols after the final cleaning stage to prevent fingerprint oils.
Packaging: Specify vacuum-sealed moisture barrier bags (MBB) with desiccant and humidity indicator cards immediately after final inspection.

Hidden risks (root causes & prevention)

Scaling production reveals weaknesses in cleaning processes that aren't visible in small prototype batches; understanding these risks allows you to implement detection gates early.

Risk: "White Haze" Residues
- Why it happens: Incomplete removal of flux residues or reaction between cleaning agents and flux.
- Detection: Visible under UV light or angled lighting; fails solvent extract conductivity test.
- Prevention: Optimize wash temperature and belt speed; monitor saponifier concentration.
Risk: Electrochemical Migration (Dendrites)
- Why it happens: Ionic residues (salts, activators) left on the board combine with moisture and bias voltage to grow conductive metal filaments.
- Detection: Surface Insulation Resistance (SIR) testing; often not found until field failure.
- Prevention: Strict ionic contamination testing (ROSE test) on every lot.
Risk: Delamination of Conformal Coating
- Why it happens: Low surface energy due to residual silicone oils or mold release agents.
- Detection: Cross-hatch tape test (ASTM D3359) fails; coating peels off easily.
- Prevention: Plasma treatment or rigorous solvent cleaning prior to coating application.
Risk: Poor Wire Bond/Die Attach Strength
- Why it happens: Organic contamination on gold pads prevents proper intermetallic formation during die attach on ceramic substrates.
- Detection: Wire pull test or die shear test yields low values.
- Prevention: Plasma cleaning immediately before bonding; store in nitrogen cabinets.
Risk: Voiding in Solder Joints (LEDs/QFNs)
- Why it happens: Oxidation on thermal pads prevents solder from wetting the entire surface during LED MCPCB assembly and reflow.
- Detection: X-Ray inspection shows high void percentage (> 25%).
- Prevention: Aggressive acid clean or micro-etch of copper prior to OSP/ENIG finish; optimized reflow profile.
Risk: "Black Pad" in ENIG
- Why it happens: Hyper-corrosion of the nickel layer during immersion gold plating, often exacerbated by poor pre-cleaning or aggressive micro-etching.
- Detection: Brittle solder joints that fracture at the intermetallic layer.
- Prevention: Strict control of the nickel bath chemistry and pre-dip cleaning steps.
Risk: Entrapped Chemistry in Vias
- Why it happens: Cleaning solution gets trapped in small vias or under low-standoff components and isn't rinsed out.
- Detection: Corrosion appearing around vias weeks after assembly.
- Prevention: Use of high-pressure spray jets; proper baking; design vias not to trap liquids (tenting/plugging).
Risk: Re-contamination from Packaging
- Why it happens: Clean boards are placed in bags that contain slip agents or silicone oils (common in cheap pink poly bags).
- Detection: Solderability issues after storage; surface energy drops.
- Prevention: Audit packaging materials; specify "silicone-free" and "amine-free" bags.

Validation plan (what to test, when, and what “pass” means)

You cannot rely on a Certificate of Compliance alone; establish a validation plan that correlates test data with physical reliability.

ROSE Test (Resistivity of Solvent Extract)
- Objective: Measure gross ionic contamination.
- Method: IPC-TM-650 2.3.25. Immerse board in IPA/water solution and measure resistivity change.
- Acceptance: < 1.56 µg/cm² NaCl equivalent.
Ion Chromatography (IC)
- Objective: Identify specific ionic species (Chloride, Bromide, Sulfate).
- Method: IPC-TM-650 2.3.28. More sensitive than ROSE.
- Acceptance: Chloride < 0.75 µg/cm²; Bromide < 0.75 µg/cm².
Surface Insulation Resistance (SIR)
- Objective: Verify electrical reliability under heat and humidity.
- Method: IPC-TM-650 2.6.3.7. Apply bias voltage in a humidity chamber (85°C/85% RH) for 168+ hours.
- Acceptance: Resistance remains > 100 MΩ; no dendritic growth visible.
Wetting Balance Test
- Objective: Quantify solderability of pads/holes.
- Method: J-STD-003. Dip sample in solder and measure wetting force vs. time.
- Acceptance: Zero crossing time < 1 second; positive wetting force.
Dyne Pen / Contact Angle Measurement
- Objective: Verify surface energy for coating/bonding adhesion.
- Method: Apply dyne fluid or measure water droplet angle.
- Acceptance: Fluid does not bead up for 2 seconds (target > 38-40 dynes).
Tape Test (Cross-Hatch)
- Objective: Check adhesion of solder mask or conformal coating.
- Method: ASTM D3359. Cut grid pattern, apply tape, pull off.
- Acceptance: 5B rating (0% removal).
Die Shear / Wire Pull Test
- Objective: Validate surface prep for die attach on ceramic substrates.
- Method: MIL-STD-883. Apply force to shear die or pull wire.
- Acceptance: Meets minimum force requirements based on die/wire size; failure mode should be in bulk material, not interface.
X-Ray Void Analysis
- Objective: Check for outgassing/wetting issues in LED MCPCB assembly and reflow.
- Method: Automated X-Ray Inspection (AXI).
- Acceptance: Total void area < 25% (or < 10% for high-power thermal applications).

Supplier checklist (RFQ + audit questions)

Use this checklist to vet potential partners like APTPCB. A supplier who cannot answer these questions likely lacks the process control for high-reliability cleaning.

RFQ Inputs (What you send)

Defined ionic contamination limit (e.g., < 1.56 µg/cm²).
Requirement for DI water rinse (specify resistivity).
Solderability standard (J-STD-003 Class 2 or 3).
Specific areas requiring plasma treatment (if applicable).
"No-Clean" vs. "Water Wash" flux specification.
Requirement for vacuum packaging with desiccant.
Prohibition of silicone-containing packaging materials.
Request for Ion Chromatography report on First Article.

Capability Proof (What they provide)

List of cleaning equipment (Inline vs. Batch, Spray pressure capabilities).
Water treatment capabilities (DI water generation and monitoring).
In-house testing equipment (Omegameter/Ionograph, X-Ray).
Experience with your specific substrate (e.g., Ceramic, Metal Core, PTFE).
Example of a cleanliness test report.
Procedure for monitoring saponifier concentration.

Quality System & Traceability

How often is the wash tank chemistry analyzed? (Daily/Shiftly).
Is there a log of water resistivity readings?
Are cleaning parameters (speed, temp, pressure) locked in the recipe?
Do they perform periodic SIR testing on test coupons?
Is there a "time-to-clean" limit after reflow? (Should be < 4-8 hours).
Are operators trained on glove protocols and handling?

Change Control & Delivery

Notification required if cleaning chemistry changes.
Notification required if flux type changes.
Shelf-life guarantee for solderability (typically 6-12 months).
Procedure for re-cleaning expired boards (if allowed).
Handling of non-conforming cleanliness results (Scrap vs. Re-wash).
Packaging audit to ensure seal integrity.

Decision guidance (trade-offs you can actually choose)

Every cleaning decision involves a trade-off between cost, process complexity, and reliability margin.

No-Clean vs. Water Wash:
- If you prioritize lowest cost and benign environments, choose No-Clean.
- If you prioritize coating adhesion and high reliability, choose Water Wash (residues must be removed).
Inline vs. Batch Cleaning:
- If you prioritize throughput for high volume, choose Inline Cleaning.
- If you prioritize cleaning under low-standoff components, choose Batch Cleaning (often has better penetration/vacuum).
Plasma Treatment vs. Chemical Clean:
- If you prioritize bonding strength for die attach on ceramic substrates, choose Plasma Treatment.
- If you prioritize general solderability, choose Chemical Micro-etch.
OSP vs. ENIG Finish:
- If you prioritize flatness and shelf life, choose ENIG (but requires strict cleaning to avoid black pad).
- If you prioritize cost and simple rework, choose OSP (but is sensitive to handling and solvents).
Standard vs. High-Purity DI Water:
- If you prioritize standard commercial electronics, standard DI water (> 1 MΩ) is acceptable.
- If you prioritize high-voltage/RF circuits, demand High-Purity DI Water (> 10-18 MΩ) to remove all conductive ions.

FAQ

Q: Can I clean "No-Clean" flux residues? A: Generally, yes, but it can be risky. Some no-clean fluxes leave white residues when partially cleaned. If you decide to clean, you must clean thoroughly with a compatible saponifier.

Q: How does surface prep affect LED MCPCBs? A: For LED MCPCB assembly and reflow, any oxidation on the aluminum/copper base or dielectric can cause delamination during the high heat of reflow. Proper cleaning ensures the thermal path remains intact.

Q: What is the shelf life of a cleaned PCB? A: Typically 6 to 12 months if vacuum sealed. Once opened, the surface finish (especially OSP or Immersion Silver) begins to oxidize and may require baking or re-cleaning before use.

Q: Why is plasma cleaning used for ceramic substrates? A: Ceramic surfaces are inert. Plasma cleaning activates the surface at a molecular level, significantly improving the bond strength for die attach on ceramic substrates and wire bonding.

Q: Is ultrasonic cleaning safe for all components? A: No. Ultrasonic energy can damage internal wire bonds in MEMS, crystals, and some ceramic capacitors. Always verify component datasheets before approving ultrasonic cleaning.

Q: How do I know if my boards are clean enough for conformal coating? A: Perform a dyne pen test. If the surface energy is below 38 dynes/cm, the coating may de-wet or peel. Cleaning is almost always required before coating.

Q: What causes "measling" after cleaning? A: Measling (white spots in the laminate) can occur if the board absorbs moisture during washing and is then exposed to thermal shock. Proper baking post-wash is the solution.

Q: Does APTPCB perform ionic contamination testing in-house? A: Yes, we perform ROSE testing and can arrange for Ion Chromatography upon request to validate compliance with your specific cleanliness standards.

PCB Surface Finishes: Understand how different finishes (ENIG, OSP, HASL) interact with cleaning processes and shelf life.
Ceramic PCB Manufacturing: Deep dive into the specific needs of ceramic boards, including plasma treatment for die attach.
Metal Core PCB (MCPCB): Learn about the thermal management requirements that make surface prep critical for LED assemblies.
PCB Conformal Coating: See why surface energy and cleanliness are prerequisites for successful coating application.
PCB Quality Control: Explore the broader quality systems and testing standards (IPC, ISO) that govern our manufacturing.

Request a quote

Ready to validate your specs? At APTPCB, we review your cleaning requirements and stackup during the DFM stage to ensure your reliability targets are met without unnecessary cost.

For the most accurate DFM and Quote, please provide:

Gerber Files: RS-274X or X2 format.
Fabrication Drawing: Clearly state ionic contamination limits and surface finish.
Assembly Notes: Specify flux type (No-Clean vs. Water Soluble) and any coating requirements.
Volume: Prototype quantity vs. production targets.
Special Processes: Mention if plasma cleaning or specific die attach steps are needed.

Conclusion

Cleaning and surface preparation is the difference between a robust product and a field failure waiting to happen. By defining clear specs for ionic contamination, validating surface energy, and auditing your supplier's process controls, you eliminate hidden risks in your supply chain. Whether you are managing complex die attach on ceramic substrates or high-volume LED MCPCB assembly and reflow, the protocols outlined here provide a roadmap to consistent quality. Treat cleanliness as a critical design parameter, and your hardware will deliver the reliability your customers expect.