From CAM review to bare-board release
PCB fabrication transforms an approved design package into a bare printed circuit board through CAM/DFM review, material preparation, imaging, lamination, drilling, metallization, solder mask, surface finish, profiling, and electrical test. Before the build starts, buyer and manufacturer should agree the stack-up, materials, tolerances, controls, acceptance criteria, and release documents. Actual capabilities, sampling, records, and timing depend on the released design and order.
Stage 1 · Data and feasibility
CAM converts the customer's released design into production artwork, drill programs, tooling, coupons, and panel instructions. DFM review checks consistency across copper, solder mask, legend, drill, profile, netlist, stack-up, and fabrication drawing; it also identifies geometry, registration, copper balance, panelization, or special-process risks before material is committed.
Buyer input
State revision, units, finished board dimensions, stack-up proposal, finished copper, finished hole sizes, tolerances, controlled-impedance structures, surface finish, mask, marking, panel delivery, test coverage, applicable standards, and required reports. Use the PCB stack-up guide and controlled-impedance guide to make critical requirements explicit.
Approval boundary
The manufacturer should return questions that change geometry, netlist, material, panel, test method, or acceptance criteria. Record every approved deviation and release one manufacturing baseline. Procurement, design, quality, and the fabricator can then evaluate the same product instead of reconciling assumptions after the build starts.
Stage 2 · Technical baseline
This release matrix separates customer intent from manufacturing verification and the evidence needed to keep the order controlled.
| Decision | Customer input | Fabrication review | Release evidence |
|---|---|---|---|
| Data package and revision | Gerber, ODB++, or IPC-2581; drill; netlist; drawing; units; revision | Layer mapping, polarity, scale, drill spans, profile, netlist, and drawing consistency | Released dataset and resolved CAM question log |
| Stack-up and layer function | Layer count, finished thickness, planes, critical signals, and dielectric constraints | Buildable construction, core and prepreg availability, symmetry, and resin flow | Approved stack-up with revision |
| Base materials | Material family or specification, relevant properties, and substitution rules | Available construction, process compatibility, and laminate supplier data | Approved material and permitted alternatives |
| Starting and finished copper | Required copper weight or thickness by layer and any selective areas | Etch, plating, spacing, thermal balance, and finished-thickness effects | Finished-copper table and CAM notes |
| Controlled impedance | Target, tolerance, structure, layer, reference plane, and report requirement | Model against the proposed stack-up, allowable CAM adjustment, and representative coupon | Approved impedance table and verification plan |
| Holes and via architecture | Finished size, plated or non-plated status, blind/buried/microvia/backdrill spans, and tolerances | Drill method, aspect ratio, registration, fill, planarization, and lamination sequence | Released tool table and via-structure map |
| Mask, finish, profile, and panel | Openings, keep-outs, finish, edge contacts, dimensions, array, breakaways, fiducials, and marking | Compatibility with fabrication, assembly, handling, profiling, and delivery format | Approved fabrication and panel drawings |
| Inspection, test, and documents | Acceptance standard, class, exceptions, sampling, tests, reports, traceability, and retention | Applicable methods, representative samples, data format, and order-specific availability | Control plan and release-document list |
If a choice changes process route, cost, risk, or schedule, close it before production authorization and record it in the order baseline.
Stages 3–8 · Inner layers and lamination
Each step has a dominant failure mode and a release signal. The exact equipment and parameters depend on the material system and construction.
Action: generate production artwork, tooling, drill programs, coupons, and panel instructions from the released dataset. Risk: revision, polarity, scale, layer-order, or netlist mismatch. Evidence: CAM checklist and comparison plots when required by the approved workflow.
Action: transfer the circuit pattern to copper, develop the resist, and remove unwanted copper. Risk: over-etch, residue, undercut, or variation that changes trace and space geometry. Evidence: process checks and agreed measurements on critical features.
Action: compare the physical inner-layer image with CAM data before the layer is buried. Risk: opens, shorts, foreign copper, or geometry defects surviving into lamination. Evidence: inspection status and documented disposition of detected anomalies.
Action: prepare copper surfaces and stack cores, prepreg, and foil in the approved sequence. Risk: wrong material, orientation error, contamination, or insufficient resin distribution. Evidence: material identification and lot-linked lay-up record.
Action: consolidate the stack with a cycle matched to the construction and resin system. Risk: voids, delamination, thickness variation, or registration outside the agreed limit. Evidence: cycle records and post-lamination checks defined by process control.
Action: locate internal targets and verify thickness, panel condition, and alignment before drilling. Risk: annular breakout or insufficient connection to inner layers. Evidence: measurements, coupons, or microsections when required by the drawing or control plan.
Stage 9 · Vertical interconnects
Drilling creates plated through holes, non-plated holes, slots, and via structures. Microvias and some blind or buried via builds can require laser drilling and sequential lamination. Backdrilling adds a depth relationship to the connected layer. The process cannot be selected from nominal hole diameter alone; it depends on the complete stack-up and connection structure.
DFM risks to close
Ambiguous finished versus tool diameter, drill-to-copper clearance, aspect ratio, registration, via span, fill, planarization, and backdrill depth can change feasibility and cost. Put these requirements in the fabrication drawing and drill legend. See the PCB drilling guide for the inputs that should accompany an RFQ.
Release evidence
The tool table, via map, backdrill rules, finished dimensions, and verification method should match the approved revision. Dimensional results, microsections, or coupons are included only when the drawing, control plan, or order calls for them.
Stages 10–11 · Hole preparation and copper
After drilling, the hole wall must be cleaned and conditioned so inner-layer copper is correctly exposed. Desmear and surface-treatment chemistry must suit the dielectric system; one recipe does not fit every FR-4, high-speed, RF, or flexible material.
Deposition and electroplating
An initial conductive deposit makes the hole wall plateable, then electroplating builds copper to the requirement defined by the drawing and applicable specification. Current distribution, panel geometry, agitation, and solution control influence uniformity, particularly in the most demanding holes in the build.
Risk and evidence
Resin residue, voids, interconnect separation, or insufficient copper can affect continuity and thermal-cycle endurance. Verification may include process records, thickness measurement, and microsectioning with agreed sampling and acceptance limits. IPC-6012 is a qualification and performance specification for rigid printed boards; class, revision, exceptions, and applicability must be stated in the order rather than inferred from a marketing claim.
Stages 12–16 · Outer layers and protection
These stages preserve electrical geometry while preparing pads, mask, markings, and mechanical features for assembly and controlled delivery.
Action: form outer-layer traces, pads, and copper features with the approved CAM sequence. Risk: width variation, undercut, shorts, or residual copper. Evidence: dimensional checks and inspection on the features and sampling defined by the control plan.
Action: apply, image, develop, and cure solder mask, then add required identification. Risk: pad encroachment, unbuildable mask dams, contamination, or ambiguous marking. Evidence: openings and text checked against released data and order criteria.
Action: protect exposed copper with the selected finish. Risk: planarity, soldering, contact, bonding, RF, or storage needs not matching the chosen finish. Evidence: finish type, selective areas, and agreed checks stated in the drawing. Compare PCB surface finishes.
Action: machine the profile, slots, and edges, clean the board, and apply required codes. Risk: dimensions outside tolerance, burrs, edge damage, contamination, or unreadable identity. Evidence: dimensional, visual, cleanliness, and marking status required by the release plan.
Surface-finish decision
The correct finish depends on pad geometry, assembly process, contact function, storage, handling, regulatory scope, and the fabricator's qualified process.
| Finish | Why it may be selected | Trade-offs to review | Confirm in the RFQ |
|---|---|---|---|
| Lead-free HASL | Cost-sensitive solderable boards where its surface profile is acceptable | Planarity and thermal exposure may not suit every fine-pitch design | Alloy, thickness expectations, pad geometry, and assembly compatibility |
| ENIG | Flat solderable surface and exposed-pad protection for many assembly flows | Nickel layer, process control, contact use, and RF loss must be evaluated by application | Applicable finish specification, nickel/gold requirements, and selective areas |
| ENEPIG | Projects combining soldering with compatible wire-bonding or contact requirements | More process steps and cost; bonding performance depends on the complete interface | Bonding method, finish stack, pad use, and acceptance method |
| Immersion silver | Flat finish where solderability or RF behavior supports the design choice | Handling, packaging, environment, and storage controls require alignment | Thickness requirement, packaging, storage window, and assembly timing |
| Immersion tin | Flat solderable finish for a compatible assembly and storage plan | Process compatibility, handling, and storage expectations must be controlled | Applicable specification, thickness, packaging, and assembly exposure |
| OSP | Thin, flat protection for copper when the assembly sequence supports it | Multiple thermal cycles, handling, inspection, and contact use need review | Chemistry, assembly cycles, storage, packaging, and exposed-contact exclusions |
Do not select a finish from a universal ranking or an assumed shelf life. Confirm the specification, thickness or process requirement, packaging, storage, and intended interface for the actual order.
Inspection, test, and release
AOI, measurement, electrical test, coupons, and documents serve different purposes. No single check proves every aspect of the finished product.
Action: compare relevant circuitry, mask, finish, and workmanship with released data and applicable criteria. Risk: assuming optical inspection detects hidden or electrical defects. Evidence: inspection status and anomaly disposition under the control plan.
Action: measure profile, holes, slots, thickness, and identified critical dimensions. Risk: using unspecified tolerances or nonrepresentative sampling. Evidence: measured results or inspection record when required by the order.
Action: test continuity and isolation against the supplied netlist and agreed limits. Risk: treating an e-test pass as functional validation of an assembled product. Evidence: status or report in the agreed format.
Action: measure a representative coupon when impedance verification is part of the order. Risk: coupon structure, test method, or acceptance limit not matching the routed design. Evidence: target, measured result, method, and coupon relationship defined in the plan.
Action: examine representative plated-hole, via, or layer structures when required. Risk: drawing conclusions from an undefined location or sample. Evidence: section location, preparation method, sampling, criteria, and results tied to the lot.
Action: reconcile revision, quantity, marking, deviations, test status, packaging, and required records. Risk: shipping acceptable boards with incomplete or mismatched documentation. Evidence: the release package listed in the purchase order.
Buyer, design, and quality checklist
Use these gates to keep critical requirements explicit across quotation, DFM, production authorization, process changes, and final release.
Include copper, mask, legend, drill, profile, netlist when available, stack-up, fabrication drawing, quantity, materials, via structures, impedance targets, finish, tolerances, panel delivery, test coverage, acceptance standards, marking, packaging, and documents. Identify revision and priority. An incomplete package produces assumptions, not a production baseline.
Record DFM questions, approved CAM edits, material alternatives, panel rules, coupons, test methods, and deviations. The stack-up, drill plan, and controlled-impedance plan must all reference the same released dataset.
Confirm quantity, revision, stack-up, materials and substitution rules, performance class, tolerances, surface finish, tests, sampling, pilot or first-article requirements, release documents, and deviation authority. Price and schedule apply to this scope, not to a generic supplier capability statement.
Define which changes require notice and approval: laminate or prepreg, copper construction, stack-up, via sequence, panelization, finish process, test method, production site, tooling, or acceptance sampling. State which evidence must be repeated before the revised build is released.
IPC-2221C covers generic printed-board design requirements; IPC-6012E addresses qualification and performance for rigid printed boards; IPC-A-600K provides printed-board acceptability criteria; IPC-9252B covers electrical testing of unpopulated boards; IPC-SM-840E addresses permanent solder-mask qualification and performance; IPC-2581 defines manufacturing-data exchange. IPC-TM-650 contains test methods that may be invoked by a specification or order. Confirm revision, class, method, exceptions, and responsibility in the contract: naming a standard alone does not prove certification or compliance.
Questions before order release
Controlled collaboration across locations
Time zone, language, and logistics may change, but revision, approvals, deviations, acceptance criteria, and release evidence should remain traceable in the order package.
Separate the product baseline from a previous supplier's internal process assumptions, then approve material, panel, tooling, test, and documentation equivalence before transfer.
Identify the applicable drawing, standard revision, customer exceptions, material rules, and required records so quotation and acceptance use the same criteria.
Align material availability, authorized alternatives, data format, build sequence, inspection plan, and delivery terms before confirming production scope.
Design, procurement, quality, and manufacturing teams should reference one released revision with named owners for approvals and deviation decisions.
Send fabrication data, drill files, stack-up, drawing, quantity, and test requirements. We will scope the quote and DFM questions against the actual build rather than a generic capability list.
