Rigid Multilayer · 4–32 Layers
Rigid PCB Fabrication & Manufacturing
APTPCB is a specialized rigid PCB fabrication manufacturer delivering prototype to production builds. Stackup, material selection, copper balance, drill registration, impedance modeling, and testing plans are verified during DFM prior to fabrication release. Buyers comparing rigid PCB suppliers evaluate the same evidence set, so the stackup, drill data and acceptance criteria are released with each build. As a China-based PCB fabricator, APT runs rigid fabrication in-house, so buyers sourcing from Europe or North America work directly with the factory.
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Precision Rigid PCB Fabrication & Board Manufacturing
Which Rigid PCB Architecture Fits Your Project?
| Architecture | Best Suited When | Clarify Before Layout Freeze |
|---|---|---|
| Standard-Rigid / Multilayer | Conventional through-hole vias, moderate routing density, and standard FR-4 cost targets are sufficient | Layer assignment, finished thickness, copper distribution, hole chart, surface finish, and panel array |
| HDI / SBU | Fine-pitch BGAs (≤0.5 mm), ultra-dense routing, or tight layer transitions require laser microvias and sequential lamination | Build-up structure (1+N+1 to 3+N+3), microvia aspect ratio, capture pads, via-in-pad copper plating, and press cycles |
| High-Speed / Controlled Impedance | High-frequency digital signals, low-loss transmission lines, or stringent signal integrity budgets govern the design | Target ohms, tolerance (±7% or ±5Ω), reference planes, laminate Dk/Df, copper foil roughness, coupon specs, and TDR plan |
| RF / Microwave | Dielectric constant stability, low loss tangent, phase consistency, and minimal attenuation take priority over standard FR-4 | Laminate brand and grade, hybrid stackup compatibility, surface finish (ENIG/Imm-Ag), waveguide geometry, and test method |
| Heavy Copper / Power | High continuous current, thermal dissipation, or rugged power terminals drive circuit board fabrication requirements | Current capacity curve, finished copper thickness (3–10 oz), trace spacing, thermal relief, board thickness, and assembly profile |
Architectures can be engineered in combination, but are not automatically combinable without stackup review. The binding build definition is established during DFM engineering release.
DFM Verification and Stackup Approval Over Raw Parameter Claims
Rigid PCB Manufacturing Capability Baseline
| Process Area | Baseline Framework | Binding Order Release |
|---|---|---|
| Multilayer Rigid Boards | Verified manufacturing baseline 4–32 layers | Layer count evaluated with finished thickness, material Tg, copper weight, and lamination sequence |
| Stackup and Materials | Standard FR-4, mid-Tg, high-Tg (Tg ≥170°C), low-loss, and high-frequency RF laminates | Specific laminate part number, supply availability, Dk/Df test condition, copper foil profile, and approved substitutes |
| Conductor Geometry | Minimum 75/75 µm (3/3 mil) trace width and spacing on baseline outer layers | Line width, spacing, annular ring, copper-to-edge clearance, and etching factor confirmed per layer |
| Drilling and Vias | 0.15 mm mechanical drill, 0.075 mm laser microvias, blind, buried, and via-in-pad | Drill aspect ratio (up to 12:1 mechanical), capture pad dimensions, resin filling, planar capping, and press cycles |
| Controlled Impedance | Single-ended (50Ω) and differential pairs (90Ω, 100Ω) modeled via field solvers | Target impedance, ±7% (>50Ω) or ±5Ω (≤50Ω) tolerance, reference planes, coupon layout, and TDR report scope |
| Copper & Power Handling | Inner and outer copper weights from 0.5 oz to heavy copper configurations | Current-carrying cross section, thermal vias, copper balance, plating distribution, and prepreg resin fill |
| Mechanical & Surface Finish | CNC routing, V-scoring, counterbores, beveling, ENIG, HASL lead-free, Immersion Silver/Tin, ENEPIG | Milling tolerances (±0.10 mm), coating thickness, solder mask registration, peelable mask, and packaging |
| Prototype to Production | NPI prototype runs, pilot lots, and volume scaling with consistent toolsets | Quoted price and lead time confirmed after complete fabrication data, DFM sign-off, and order approval |
Baseline parameters serve as planning guidelines. Demanding combinations are evaluated holistically across the complete build package.
Six Engineering Release Gates Before Production Launch
| Release Gate | Verified Prior to Fabrication | Gate Deliverable |
|---|---|---|
| 1. Data Package & Revision | Gerber/ODB++/IPC-2581, NC drill, netlist, drawing, and readme carry matched revision codes | Unambiguous fabrication data package released to CAM |
| 2. Stackup & Material Selection | Layer sequence, dielectric thicknesses, copper foils, finished thickness, laminate grade, and CoC needs | Approved stackup drawing with documented modeling assumptions |
| 3. Drill & Via Architecture | PTH/NPTH hole sizes, microvias, via plugging, capping, backdrill depth, and annular ring margins | Validated drill table and lamination sequence plan |
| 4. Electrical Requirements & Impedance | IPC-D-356 netlist, impedance targets, reference layers, CAM trace adjustment rights, and coupon rules | Reconciled electrical manufacturing and testing foundation |
| 5. Mechanical Routing & Panelization | Outline dimensions, routing path, scoring, tabs, slots, bevels, fiducials, and assembly rails | Approved mechanical drawing and production panel layout |
| 6. Quality & Inspection Plan | Bare-board electrical test (IPC-9252), AOI, microsection, TDR log, dimensional report, and CoC scope | Contracted quality evidence plan with defined acceptance criteria |
What Drives Rigid PCB Manufacturing Cost and Lead Time
| Cost Driver | Root Engineering Impact | Proactive Design Control |
|---|---|---|
| Layer Count & Lamination Cycles | Higher layer counts and multiple press cycles increase process steps, inner-layer AOI, and registration risk | Compare routing density against layer count and via types before freezing layout |
| Material Selection & Stackup Availability | Specialty RF/high-speed laminates and tight dielectric tolerances require specific procurement windows | Specify functional requirements (Tg, Dk, Df) and list pre-approved material alternates |
| Trace Geometry & Drill Aspect Ratio | Fine traces (<75 µm), small annular rings, and high aspect ratios reduce CAM process margins and yield | Apply fine geometries selectively on dense signal layers; avoid blanket extreme rules |
| Copper Weight & Surface Finish | Heavy copper requires extended etching and resin fill; finishes like ENEPIG involve multiple plating baths | Specify heavy copper only where thermal or current loads mandate it; match finish to assembly needs |
| Panel Utilization & Volume Model | Sub-optimal board dimensions yield low panel area efficiency, increasing per-board laminate overhead | Coordinate board outline with standard production panel sizes and include annual volume forecasts |
| Inspection & Documentation Scope | Microsections, serialised TDR testing, first-article reports, and raw material CoCs require manual processing | Align inspection and documentation scope to actual mission-critical project risks |
Rigid PCB RFQ Checklist for First-Time-Right Quoting
| Input Requirement | Required Data & Specifications | Engineering Purpose |
|---|---|---|
| Manufacturing Files | Gerber X2, ODB++, or IPC-2581; NC drill files; IPC-D-356 electrical netlist | Prevents discrepancies between optical copper layers, drill data, and intended connectivity |
| Fabrication Drawing & Revision | Formal mechanical drawing, readme file, clear part number, and revision identifier | Defines dimensions, tolerances, process notes, and official configuration baseline |
| Stackup Definition | Layer count, dielectric thicknesses, core/prepreg preferences, and copper weight per layer | Establishes lamination sequence, layer registration, impedance, and overall board thickness |
| Laminate & Surface Finish | Base material family, Tg, Td, flammability, solder mask color, and final surface finish (e.g. ENIG, HASL) | Harmonizes thermal endurance, solderability, shelf-life, and procurement channels |
| Drill and Via Table | PTH/NPTH hole chart, blind/buried spans, microvia layers, via plugging (Type VII), and backdrill rules | Governs drilling technology, lamination stages, plating cycles, and planarization |
| Impedance & High-Voltage Spacing | Target ohms, tolerance (±7%), signal layers, reference planes, and isolation clearance limits | Enables CAM field modeling, etch compensation, and test coupon design |
| Mechanical Outline & Array | Board outline, critical dimensional tolerances, scoring angles, mouse-bites, and panel array details | Ensures compatibility with automated SMT placement, tooling pins, and final chassis fit |
| Volume, Schedule & Test Scope | Prototype/pilot quantity, target delivery date, E-test, AOI, microsection, TDR coupon, or CoC needs | Provides a transparent, comparable commercial proposal with complete deliverable scope |
Align Critical Fabrication Requirements Before Layout Freeze
Frequently Asked Questions About Rigid PCB Manufacturing
What is a rigid printed circuit board?
A rigid PCB uses a solid, non-flexible core base material to maintain structural shape throughout its operational lifecycle. Depending on electrical and mechanical constraints, it can be engineered as a standard multilayer, an HDI microvia board, an impedance-controlled high-speed digital circuit, an RF/microwave board, or a heavy copper power substrate.
How many layers does APTPCB manufacture for rigid multilayers?
Our published manufacturing range for rigid multilayer printed circuit boards spans 4–32 layers. The exact combination of layer count, laminate selection, copper balance, finished board thickness, hole aspect ratio, and panelization is verified and confirmed through engineering DFM prior to fabrication release.
Can minimum trace width, hole size, and maximum copper weight be guaranteed in isolation?
No, isolated extreme values cannot be promised without reviewing the entire design package. Trace width, spacing, annular rings, hole aspect ratios, and finished copper weight interact directly with each other and are evaluated against stackup symmetry, dielectric thickness, panel yield, and testing scope during DFM review.
When is an HDI or microvia architecture needed instead of a standard multilayer?
An HDI or sequential build-up (SBU) architecture is recommended when fine-pitch components (such as 0.4 mm or 0.5 mm pitch BGAs), tight routing channels, or high-speed layer transitions cannot be achieved with through-hole vias. Lamination cycles, microvia aspect ratios, capture pad sizes, and via-in-pad plating must be established before finalizing layout.
How is controlled impedance modeled, released, and verified?
Impedance verification requires defining target ohms, allowable tolerance (typically ±7% or ±5 ohms), trace geometry, reference planes, laminate properties (Dk/Df), and permitted CAM etching compensations. Dedicated test coupons and TDR coupon reports are included in the deliverable scope when agreed in the order.
What quality and test records can be included for rigid PCB fabrication?
Depending on project criticality and industry standards, deliverables may include netlist-driven electrical testing (IPC-9252), Automated Optical Inspection (AOI), microsection coupon analysis, TDR impedance test logs, dimensional verification, material certificates of conformance (CoC), and lot traceability reports.
What data package does APTPCB require for an accurate PCB fabrication quote?
To provide a binding quote, submit standard Gerber X2, ODB++, or IPC-2581 files along with NC drill files, IPC-D-356 netlist, fabrication drawing, layer stackup drawing, material specifications, required surface finish, impedance table, contour routing tolerances, quantity, and requested inspection scope.
What factors determine the lead time and price of a rigid circuit board?
Cost and lead time are primarily determined by layer count, sequential lamination cycles, raw material availability, drill hole density and aspect ratios, finished copper weight, surface finish, panel utilization efficiency, order volume, and specified quality inspection deliverables.
Start an Engineering-Approved Rigid PCB Fabrication Quote
Submit your Gerber data, stackup requirements, material specifications, and quality expectations. APTPCB confirms manufacturability, DFM queries, and verified deliverable scope.