1+N+1
Single build-up per side
One sequential build-up layer is added on each side of a conventional core. Release the laser-via diameter, capture pad, target layer, fill requirement, and copper finish with the stack-up.
Layer construction before routing release
PCB Stack-up Design for Manufacturable Multilayer Builds
A PCB stack-up is the ordered construction of copper layers, cores, prepregs, and special materials that determines reference planes, routing space, finished thickness, impedance geometry, and fabrication sequence. APTPCB reviews stack-ups against material, lamination, drilling, plating, thermal, and test requirements before production release.
4–32 layers
Verified rigid PCB range
±5% TDR
Impedance verification when specified
Gerber + ODB++
CAM-ready release data
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Engineering foundation
Start the PCB stack-up before final routing
Layer count alone does not define a manufacturable stack-up. The design must connect signal layers to stable reference planes, allocate dielectric spacing for impedance, provide enough copper and resin balance for lamination, and reserve a realistic drill and plating path. Early review with impedance-control requirements reduces late geometry changes.
APTPCB reviews the proposed construction against the verified 4–32 layer rigid-board range, material availability, finished thickness, copper weights, via types, sequential-lamination needs, and required evidence. The approved output should be a releaseable layer table rather than an informal sketch.
Architecture selection
Choose a PCB stack-up architecture by interconnect and material need
This comparison separates architectures by fabrication sequence and design input rather than treating every multilayer board as the same construction.
| Architecture | Typical use | Construction decision | Main release inputs | Primary risk to review |
|---|---|---|---|---|
| Rigid FR-4 multilayer | Industrial control, computing, instrumentation | Through-hole or selected blind/buried structure | Layer order, copper, thickness, material class | Plane reference, balance, drill aspect ratio |
| Low-loss digital multilayer | High-speed links and dense computing | Low-loss material and copper profile selected by channel need | Loss target, stack-up, impedance table, routing constraints | Material substitution and insertion-loss margin |
| HDI sequential build | Fine-pitch fan-out and compact routing | One or more sequential lamination cycles | Microvia layers, capture pads, fill and plating needs | Registration, stacked versus staggered vias, cycle count |
| Flex or rigid-flex | Folded interconnects and space-constrained assemblies | Polyimide flex zones joined to rigid areas as specified | Bend region, coverlay, stiffener, layer transitions | Bend reliability and transition geometry |
| Heavy-copper or thermal build | Power conversion and thermal spreading | Copper distribution and dielectric system chosen together | Current, copper weight, spacing, thermal path | Resin fill, etch capability, thickness variation |
| RF or mixed-material build | RF front ends, antennas, mixed RF/digital boards | RF laminate used only where electrical need justifies it | Frequency, Dk/Df need, copper type, bond layer | Material compatibility, registration, thickness tolerance |
Architecture feasibility depends on the complete construction. Material names, via schemes, and thicknesses remain provisional until the fabrication data and acceptance requirements are reviewed.
Rigid multilayer
Balance reference planes, dielectric spacing, and manufacturability
A rigid multilayer stack-up should give critical signals a defined reference while keeping copper distribution and dielectric construction reasonably balanced around the board center. Plane assignment, split planes, return paths, and routing transitions matter as much as the nominal number of layers.
As layer count increases within the 4–32 layer range, drill depth, registration, lamination sequence, finished thickness, and test access become stronger constraints. Back-drilling, buried vias, or special materials should be justified by an electrical or mechanical requirement and released with clear tolerances.
HDI sequence
Release the HDI via and lamination sequence together
HDI feasibility depends on which layers connect, how microvias are formed and filled, and how many lamination cycles the design requires.
2+N+2
Two build-up layers per side
Two build-up layers increase routing access but add alignment and process dependencies. Confirm HDI fabrication boundaries, then state whether microvias are staggered or stacked and whether copper filling is required.
Via map
Connection map before artwork lock
Document every blind, buried, and through-hole span. Avoid ambiguous via labels that do not identify start layer, stop layer, finished size, or fill and cap requirements.
Release
Approve sequence and evidence
Approve the proposed lamination sequence, material set, microvia structure, impedance construction, and any microsection or registration evidence before tooling release.
Flex and rigid-flex
Treat bend zones and rigid transitions as stack-up requirements
A flex or rigid-flex construction must identify which layers continue through the bend, where coverlay and stiffeners begin, how copper is oriented, and whether the bend is static or dynamic. The flex zone should not inherit rigid-board assumptions about dielectric, mask, or via placement.
Release the bend radius, flex thickness, copper type, transition geometry, stiffener locations, and assembly constraints. Review related flex PCB capability boundaries before the mechanical enclosure freezes the routing path.
Power and thermal
Copper weight and thermal path change the lamination problem
A heavy-copper construction changes spacing, etching, resin fill, pressed thickness, and drill planning. Define the actual current path, copper distribution, voltage spacing, finished copper need, and allowable temperature rise instead of selecting copper weight by a generic rule.
Metal-core and other thermal constructions require the dielectric layer, thermal path, isolation need, base material, thickness, and mechanical attachment to be reviewed as one system. Thermal PCB requirements should be separated from signal-layer stack-up assumptions.
RF and mixed materials
Use RF laminate only where the electrical requirement needs it
A mixed RF and digital stack-up can reduce material use, but it introduces compatibility questions: dielectric properties, copper profile, bond layer, thermal expansion, drilling behavior, registration, and pressed thickness must work together. The material name alone does not define the finished electrical structure.
Provide operating frequency, impedance, loss objective, RF layer, reference plane, copper requirement, finish, environmental exposure, and mechanical tolerance. Review available RF laminate options only after the required properties are clear.
Release-input matrix
Seven stack-up inputs that must agree before fabrication
Each input changes more than one downstream process, so review them as a connected release package.
| Input | What to provide | Manufacturing effect | Release evidence |
|---|---|---|---|
| Layer order | Signal, plane, power, and reference assignment | Imaging, lamination, drill map | Approved layer table |
| Material system | Named material or property requirement and substitution rule | Press cycle, drilling, electrical behavior | Approved material set |
| Copper | Starting and finished copper by layer | Etching, plating, resin fill, thickness | Copper table in stack-up |
| Dielectric spacing | Target spacing or impedance-driven construction | Pressed thickness and impedance geometry | Reviewed core/prepreg construction |
| Via structure | Start/stop layers, size, fill, cap, back-drill | Drilling, plating, lamination sequence | Released via map |
| Finished thickness | Nominal value and tolerance | Material selection and press construction | Approved stack-up thickness |
| Verification | Impedance, microsection, dimensional, or other reports | Coupon and inspection planning | Defined shipment record list |
Send the stack-up inputs before routing is frozen
Upload the proposed layer table, thickness, material requirements, copper weights, impedance table, via map, fabrication constraints, and Gerber X2, ODB++, or IPC-2581 data for engineering review.
Core and prepreg have different jobs in the stack-up
A core is a cured dielectric sheet with copper on one or both sides. Its thickness is comparatively stable and it often forms the starting image layers in a multilayer construction.
A prepreg contains partially cured resin and reinforcement. During lamination it bonds adjacent layers and flows around copper features; final pressed thickness depends on the prepreg construction, resin content, copper distribution, and press process.
For that reason, substituting one core or prepreg style can change total thickness, resin fill, impedance geometry, and material behavior. Substitution rules belong in the approved release, not in an informal purchasing note.
Select materials by required properties and availability
Start with operating temperature, electrical loss, frequency, thermal expansion, flammability requirement, moisture exposure, thickness tolerance, copper profile, and assembly process. A brand name without these constraints leaves substitution and availability risk unresolved.
For conventional multilayers, FR-4 families may satisfy the need when Tg, decomposition behavior, loss, and CAF expectations are defined. High-speed or RF layers may require lower-loss materials, while flex zones require polyimide constructions and coverlay-compatible processing.
The quotation should identify the proposed material set and any allowed equivalents. If an exact grade is mandatory, state it explicitly and account for sourcing lead time before the production date is committed.
References should be selected for the actual construction and contract: IPC-2221 for generic design, IPC-2226 for HDI, IPC-6012 for rigid boards, and IPC-6013 for flexible or rigid-flex boards. State the class, acceptance criteria, and required reports explicitly in the fabrication drawing.
Six release gates for a manufacturable PCB stack-up
1. Define references before routing
Assign signal, plane, and power layers so critical routes have continuous return paths. Identify split-plane crossings and layer transitions before the routing density consumes the available space.
2. Balance construction and copper
Review copper distribution, core and prepreg placement, and mechanical symmetry. Balance is an engineering check, not simply an equal number of layers above and below the center.
3. Release the complete via map
State every through, blind, buried, filled, capped, and back-drilled structure with start layer, stop layer, finished size, tolerance, and special processing requirement.
4. Tie impedance to the production stack-up
List target impedance, tolerance, layer, trace type, and reference plane. Approve geometry changes caused by the reviewed dielectric construction before fabrication.
5. Lock material and thickness rules
State required material properties, exact grades where mandatory, allowed substitutions, finished thickness, copper definition, and any property that must be reported with shipment.
6. RFQ input checklist
Provide release-ready fabrication data in Gerber X2, ODB++, or IPC-2581 format, plus drill data, proposed layer order, board thickness and tolerance, copper by layer, material requirements, impedance table, via map, critical dimensions, quantity, and required verification reports.
Application-driven construction
Different products stress different stack-up decisions
High-speed computing
Reference continuity and loss budget
Prioritize uninterrupted return paths, via transitions, material loss, copper profile, impedance tolerance, and the evidence required for critical channels.
RF and antenna
Material properties and thickness control
Prioritize Dk/Df need, copper roughness, bond layer, RF reference planes, finish, mechanical tolerance, and separation from noisy digital or power regions.
Power electronics
Copper, spacing, and thermal path
Prioritize current path, voltage spacing, copper distribution, resin fill, isolation, heat spreading, assembly temperature, and mechanical attachment.
Compact electromechanical
HDI or flex routing boundaries
Prioritize fine-pitch escape, microvia sequence, bend region, flex thickness, stiffeners, component keep-outs, enclosure clearance, and assembly handling.
Stack-up FAQ
PCB stack-up questions before fabrication release
What is a PCB stack-up?
A PCB stack-up is the ordered construction of copper layers, cores, prepregs, and special material layers that defines thickness, reference planes, routing space, impedance behavior, and fabrication sequence.
When should the fabricator review the stack-up?
Review should start before routing is locked. Early review allows dielectric thickness, copper weight, material availability, impedance geometry, via structure, and total thickness tolerance to be aligned before release.
What files are needed for a PCB stack-up review?
Provide the proposed layer order, board thickness, copper weights, material or performance requirements, impedance table, via types, drill data, critical mechanical limits, and Gerber X2, ODB++, or IPC-2581 data when available.
Why should a multilayer stack-up be symmetric?
A balanced construction helps manage mechanical stress and bow or twist. Copper distribution, dielectric spacing, material type, and sequential-lamination features still need engineering review rather than symmetry by layer count alone.
How are controlled-impedance values released?
Release the target impedance, tolerance, layer, trace type, reference plane, and relevant geometry. The reviewed production stack-up and coupon requirement should be approved before fabrication, with TDR evidence requested when needed.
What is the difference between core and prepreg?
A core is a cured dielectric with copper on one or both sides. Prepreg is resin-impregnated reinforcement used to bond layers during lamination; its pressed thickness and resin behavior depend on construction and copper distribution.
When does a stack-up require sequential lamination?
Sequential lamination is commonly required when blind or buried interconnects cannot be formed in one conventional lamination cycle. The via sequence, capture layers, plating, fill, and registration plan must be reviewed together.
Can RF material be combined with FR-4?
A mixed-material construction may be possible, but dielectric properties, copper type, bond layer, thickness tolerance, thermal expansion, drilling, plating, and lamination compatibility must be reviewed for the actual material set.
How is finished PCB thickness controlled?
Finished thickness is built from cores, pressed prepregs, copper, and surface finish. The drawing should state the nominal thickness and tolerance, while the reviewed stack-up identifies the construction used to meet it.
What should be approved before stack-up release?
Approve the layer order, materials, copper weights, dielectric spacing, total thickness, impedance targets, via and lamination sequence, special process notes, allowed substitutions, and required verification reports.
Remote engineering review
A stack-up package that distributed teams can approve
Keep layer, material, impedance, via, and thickness decisions in one reviewable release package across locations and suppliers.
North America
High-speed and compute programs
Release reference planes, loss needs, impedance structures, via transitions, back-drill requirements, and channel evidence before routing sign-off.
Europe
Industrial and regulated programs
Release material restrictions, traceability, thickness tolerance, acceptance criteria, change rules, and the reports required for design records.
Asia-Pacific
Dense and repeat builds
Keep the same approved construction tied to tooling, panelization, impedance coupons, and repeat-order data when quantities or factories change.
Middle East
RF and high-reliability programs
Release material properties, RF reference structures, environmental limits, special inspection, and final system responsibility before quotation.
Review the PCB stack-up before fabrication release
Upload the proposed layer table, board thickness, copper weights, material requirements, impedance table, via map, Gerber X2, ODB++, or IPC-2581 data, and required reports.