An IGBT gate driver PCB translates low-voltage control commands into controlled gate current while isolating domains, detecting faults and preventing unintended switching. It must be designed with the specific IGBT/module, DC-link voltage, commutation loop, switching frequency, gate-charge target, cooling and protection timing.
Key takeaways
- Keep the gate-source drive loop short and separate from the power-emitter path; use the module's Kelvin emitter where provided.
- Select turn-on and turn-off resistance from measured switching behavior, not a universal value.
- Coordinate DESAT blanking, soft shutdown, negative bias and Miller clamp with short-circuit withstand and system protection.
- Design isolation from working voltage, transient stress, dv/dt, lifetime, pollution, altitude and applicable standards.
- Validate at the real module, bus voltage, current, temperature and parasitic layout using safe double-pulse or inverter testing.
- Production test should verify isolated supplies, propagation, UVLO, gate levels and protection without applying uncontrolled high energy.
Gate-loop layout and switching control
The driver, gate resistor, IGBT gate and Kelvin emitter form the critical loop. Parasitic inductance causes gate ringing, voltage overshoot and common-emitter feedback.
- Place the driver and gate components close to the module connector.
- Route gate and Kelvin return together with minimal loop area.
- Keep the power-emitter current out of the driver return.
- Separate turn-on/turn-off resistors or active gate control if different slew rates are needed.
- Provide measurement points that do not add unsafe stubs during normal operation.
- Control connector pinout so gate and return remain adjacent.
- Keep DESAT and fault nets away from switching nodes.
Fast switching reduces loss but increases dv/dt, EMI, overshoot and false turn-on risk. Tune against system limits for collector voltage, current, diode recovery, insulation stress, EMI and thermal loss.
Prevent parasitic turn-on
Collector dv/dt drives current through the Miller capacitance. If the gate path impedance is too high, gate voltage can rise above threshold.
Mitigations include low-impedance turn-off, negative gate bias, active Miller clamp, optimized layout and appropriate dead time. Each affects driver supply, device stress and fault behavior; verify the actual gate waveform at temperature.
DESAT and short-circuit protection
DESAT protection monitors collector-emitter behavior after turn-on. It needs a blanking interval for normal switching and diode recovery, then a controlled response fast enough for the IGBT's short-circuit capability.
| Design item | Risk if wrong |
|---|---|
| DESAT diode voltage/behavior | Incorrect threshold or slow recovery |
| Blanking time | False trip or delayed fault detection |
| Filter/leading-edge suppression | Noise trip or hidden fault |
| Soft shutdown | Excess overvoltage if too fast; excess energy if too slow |
| Fault latch/reset | Repetitive destructive restart |
| UVLO | Partial enhancement and high loss |
Coordinate driver protection with current sensing, DC-link protection, controller logic, contactors/fuses and discharge. Do not claim a universal microsecond response without the device and circuit conditions.
Isolated power and signal integrity
The isolated supply must provide the required positive/negative gate rails, peak current, average gate-charge power and transient response. Its interwinding capacitance can inject common-mode current during switching.
- Select isolator/transformer CMTI for the expected dv/dt with margin.
- Keep primary and secondary current loops compact.
- Filter the local gate supply close to the driver.
- Define startup/shutdown so the IGBT stays off during rail sequencing.
- Verify propagation delay and channel matching where bridge timing matters.
- Control creepage/clearance, slots and barrier components as one insulation system.
- Review partial discharge and reinforced/basic insulation requirements where applicable.
Assembly and production controls
- Exact driver, isolator, DESAT diode and gate-resistor identity
- High-voltage component spacing and solder-mask/slot inspection
- Transformer orientation and isolated-supply testing
- Connector coplanarity, retention and pinout verification
- SPI/AOI and X-ray for hidden joints where required
- Cleanliness across high-impedance and isolation areas
- Controlled coating mask and cure where used
- Serialized hardware, firmware/configuration and test records
Use turnkey PCB assembly with an approved BOM; substitutions in isolators, DC/DC modules, diodes or gate components can change CMTI, delay and protection behavior.
Validation matrix
- Bare-board electrical and insulation-feature inspection
- Assembly inspection and current-limited power-up
- Isolated supply rails, ripple, UVLO and sequencing
- Input/output logic, propagation delay and dead-time checks
- Gate amplitude, source/sink behavior and fault output with dummy loads
- DESAT threshold/blanking and soft-shutdown fixture test
- Double-pulse or inverter test at controlled voltage/current and temperature
- Short-circuit/protection validation only in a purpose-built safe setup
- EMC, thermal and environmental qualification on the complete converter
High-energy tests require interlocks, remote operation, shielding, discharge verification and trained personnel.
IGBT gate driver PCB RFQ checklist
- IGBT/module, bus voltage, current, switching frequency and topology
- Gate-voltage targets, gate charge, resistors, negative bias and Miller strategy
- DESAT/short-circuit, UVLO, fault/reset and soft-shutdown requirements
- Isolation working/transient voltage, CMTI, insulation class and altitude
- PCB files, stack-up, slots, coating, connectors and mechanical interface
- BOM/alternates, assembly, cleaning and traceability
- Dummy-load, timing, protection and high-energy validation scope
- Quantities, first article, change notification and schedule
Submit the controlled package through the PCB quotation page and define which high-energy tests remain at system level.
Standards and scope
- IEC 61800-5-1 — Adjustable speed electrical power drive systems, safety
- IEC 60664-1 — Insulation coordination
- IEC 60747 series — Semiconductor devices
- IEC 61000-4 series — EMC immunity tests
- IPC-2221, IPC-6012, J-STD-001 and IPC-A-610
Confirm application-specific editions and certification requirements. Gate-driver PCBA manufacturing does not independently certify the inverter, motor drive, traction converter or power system.
IGBT gate driver FAQ
Why use a Kelvin emitter connection?
It gives the driver a return path separated from high power-emitter current, reducing common-emitter inductance feedback and gate-voltage distortion.
Is negative gate bias always required?
No. It depends on device threshold, dv/dt, Miller coupling, layout, driver impedance and system risk. Validate the selected off voltage against the IGBT datasheet and measured switching.
What does DESAT protection do?
It detects abnormal collector-emitter voltage after turn-on, indicating that the IGBT may be leaving saturation during overcurrent or short circuit, then initiates a controlled shutdown.
Can gate resistance be chosen from a reference design?
It is a starting point only. Tune it using the actual module, bus, commutation path, temperature and switching limits.
What files are needed for assembly quotation?
Provide controlled PCB/BOM/placement files plus module interface, isolation, gate/protection targets, test procedures, quantities and approved substitutions.