A CoWoS package connects advanced logic and high-bandwidth memory through an interposer-based package structure, then transitions through an organic carrier substrate into the system PCB. These layers solve different engineering problems and require different manufacturing capabilities.
The silicon interposer, redistribution layers, organic package substrate, and accelerator motherboard are separate design domains. A successful AI or HPC system depends on controlling the handoff between them: package geometry, BGA interface, power delivery, signal routing, thermal constraints, mechanical loading, and qualification evidence.
What is the difference between a CoWoS package substrate and a system PCB?
A CoWoS carrier substrate is part of the semiconductor package. It provides fine-pitch redistribution between the advanced package interconnect and the external BGA interface.
The system PCB is the board-level platform that connects the package to power delivery, networking, storage, connectors, and the rest of the system.
| Product layer | Typical owner | Engineering information transferred |
|---|---|---|
| Logic/HBM dies and microbump interface | Chip, foundry, and package teams | Die arrangement, thermal requirements, interconnect requirements |
| Silicon interposer or RDL interconnect layer | Advanced packaging provider | Fine routing structure, bump interface, process constraints |
| Organic carrier substrate | Package substrate and OSAT ecosystem | Build-up technology, BGA map, warpage data, package qualification |
| System/accelerator PCB | Hardware OEM and PCB supplier | Stack-up, escape routing, power planes, connectors, board qualification |
| Cooling and mechanical assembly | Mechanical/system team | Heat sink, cold plate, retention, loading, flatness requirements |
A conventional PCB fabrication drawing is not a replacement for package-substrate design data. The PCB supplier needs the released package interface information before board architecture decisions are finalized.
What CoWoS package data does a PCB designer need?
Before routing begins, the system team should receive controlled package information covering mechanical, electrical, thermal, and manufacturing requirements.
| Input category | Required information |
|---|---|
| Mechanical interface | Package outline, height, mass, keepout area, mounting constraints |
| BGA interface | Ball map, pitch, pad recommendation, escape restrictions |
| Signal integrity | Channel models, high-speed I/O constraints, reference-clock requirements |
| Power delivery | Power-domain map, transient requirements, target impedance |
| Thermal design | Power map, thermal model, operating limits |
| Assembly | Reflow profile, underfill/socket limits, cleaning and rework restrictions |
| Reliability | Warpage, coplanarity, handling, storage, traceability requirements |
Without controlled package inputs, PCB layer count, via structure, impedance targets, and power-delivery performance remain preliminary.
How should engineers separate CoWoS design ownership?
A clear ownership boundary prevents incorrect sourcing decisions.
- Semiconductor and packaging teams control interposer technology, microbump structures, package assembly, and package qualification.
- Package-substrate suppliers control organic substrate fabrication, fine-pitch routing, and package-level manufacturing processes.
- System PCB suppliers control motherboard fabrication, HDI structures, copper distribution, board-level signal integrity, and production testing.
The correct RFQ scope depends on the physical interface being manufactured.
How do CoWoS packages affect PCB escape routing and signal integrity?
Large AI accelerator packages create dense BGA fields with demanding escape requirements. Board routing must translate the package interface into manufacturable PCB structures while preserving signal quality.
Key design decisions include:
- Reserve power and ground access before optimizing signal escape density.
- Maintain controlled return paths for high-speed interfaces.
- Model BGA pads, antipads, breakout structures, and via transitions.
- Control residual via stubs through appropriate via strategies.
- Include package, PCB, connector, and cable contributions in the channel budget.
- Define TDR and VNA coupon structures that represent the actual production stack-up.
Use high-speed PCB manufacturing and HDI PCB capability to evaluate the system-board build, not semiconductor package-substrate fabrication.
How should engineers evaluate CoWoS power delivery and thermal design?
AI and HPC packages create high current demand, fast transient behavior, and concentrated heat loads. Power integrity and thermal-mechanical design must be reviewed together.
Important design inputs include:
- power and ground distribution through the package interface;
- breakout inductance from package balls to PCB planes;
- decoupling placement based on frequency response and connection inductance;
- VRM-to-package impedance targets;
- copper distribution and temperature rise;
- heat sink or cold-plate loading;
- stiffener and retention effects;
- board deformation under assembly and operation.
A stable design considers the entire package-board-cooling structure rather than treating the PCB as an isolated component.
What CoWoS interface risks require qualification evidence?
| Failure mode | Interface cause | Useful evidence |
|---|---|---|
| BGA non-wet or open connection | Package/board warpage, solder process mismatch, pad design issue | Warpage measurement, assembly profile, X-ray, cross-section |
| Pad cratering or board strain | Mechanical retention, handling, cooling load | Strain measurement, mechanical analysis |
| Power droop or noise | Plane inductance, breakout structure, insufficient decoupling, VRM response | PDN simulation, impedance measurement, transient testing |
| Channel margin loss | Via discontinuity, excessive loss, crosstalk, return-path disruption | Channel simulation, TDR/VNA, BER testing |
| Thermal throttling | Cooling path, TIM interface, airflow or liquid-cooling limitation | Thermal model and system measurement |
| Solder fatigue | CTE mismatch, warpage, thermal cycling, board stiffness | Reliability cycling and failure analysis |
What manufacturing controls matter for a CoWoS system PCB?
The system PCB production process should lock the interface details that affect package assembly.
Important controls include:
- laminate selection and approved substitutions;
- copper thickness and profile;
- HDI and backdrill structures;
- BGA registration and antipad geometry;
- via-in-pad fill and cap requirements;
- board flatness and local coplanarity;
- surface-finish compatibility;
- SPI, AOI, X-ray, and CT inspection strategy;
- boundary scan, power testing, high-speed loopback, BER testing, and thermal telemetry.
Rework limits should be established with the package owner before production begins.
How do engineers select the right CoWoS PCB supplier?
A supplier evaluation should distinguish package-substrate capability from system-board capability.
| Evaluation item | Supplier decision question |
|---|---|
| Manufacturing scope | Does the supplier quote system PCB, package substrate, test board, or another interface product? |
| HDI capability | Can the supplier build the required via structures and registration tolerances? |
| High-speed capability | Can the supplier validate impedance, loss, and channel performance? |
| Power delivery support | Can the supplier support copper structures and validation requirements? |
| Assembly knowledge | Does the supplier understand advanced BGA assembly constraints? |
| Quality evidence | Are inspection, traceability, and reliability records available? |
| Engineering support | Can the supplier review stack-up, SI/PI, and manufacturability risks? |
A qualified system PCB partner should demonstrate capability for the released interface, not claim ownership of semiconductor package processes outside its manufacturing scope.
What should a CoWoS PCB RFQ package contain?
A complete RFQ package should include:
- package vendor, part number, and revision;
- package outline and BGA land-pattern information;
- electrical, thermal, and mechanical models under NDA when required;
- PCB stack-up requirements;
- laminate, copper profile, and impedance targets;
- escape routing, HDI, via, and backdrill requirements;
- power map, PDN targets, and VRM interface information;
- cooling, retention, and board-strain constraints;
- placement, BOM, and test requirements;
- first article, traceability, and change-notification requirements;
- clear manufacturing scope statement.
Submit conventional PCB/interface-board requirements through the PCB quotation page. Advanced package-substrate scope belongs with qualified semiconductor packaging suppliers.
Which standards apply to CoWoS system PCB qualification?
Relevant standards and references include:
- JEDEC JESD235 series — High Bandwidth Memory
- JEDEC JESD22 series — Semiconductor device reliability test methods
- IPC-6012 — Qualification and performance for rigid printed boards
- IPC-9701 — Performance test methods and qualification requirements for surface-mount solder attachments
- IEEE 1149.1 — Boundary-scan test access, where implemented
Package-provider requirements and current standard revisions should be confirmed for each program. “Industrial-grade CoWoS” is not a standalone PCB material category or universal qualification standard.
CoWoS carrier substrate FAQ
Is a CoWoS carrier substrate the same as a multilayer PCB?
No. The organic carrier substrate is part of an advanced semiconductor package and uses package-level manufacturing processes, fine routing structures, and qualification methods beyond conventional PCB fabrication.
Can a PCB manufacturer build the CoWoS silicon interposer?
Not as a normal PCB order. Interposer, RDL, and advanced package assembly processes belong to qualified semiconductor packaging supply chains.
What can a system PCB supplier manufacture?
A system PCB supplier can manufacture accelerator boards, evaluation boards, interface boards, and other board-level hardware when provided with the released package interface data.
Why is CoWoS warpage important?
Package and board warpage affect solder contact, assembly yield, and mechanical reliability. The package, PCB, and cooling structure must be evaluated together.
What information is required before PCB routing starts?
The minimum dataset includes package outline, BGA map, land pattern, electrical models, thermal information, power requirements, and assembly constraints.