Rdl Fan-Out Substrate Checklist: Complete Design Guide & DFM Specs

Redistribution Layer (RDL) fan-out substrate checklist quick answer (30 seconds)

RDL fan-out substrate checklist quick answer (30 seconds)

Redistribution Layer (RDL) fan-out technology bridges the gap between silicon dies and printed circuit boards by creating high-density interconnections without a traditional package substrate. To ensure yield and reliability, engineers must validate specific parameters during the design and manufacturing phases.

Line/Space (L/S) Constraints: Verify minimum trace width and spacing, typically ranging from 2µm/2µm to 10µm/10µm depending on the lithography process.
Dielectric Material Selection: Confirm the use of Photosensitive Polyimide (PSPI) or PBO (Polybenzoxazole) for proper elongation and cure temperature compatibility.
Via Aspect Ratio: Ensure photo-via aspect ratios remain below 1:1 or 1.5:1 to guarantee complete plating and electrical continuity.
Warpage Control: Validate Carrier CTE (Coefficient of Thermal Expansion) and molding compound properties to prevent panel/wafer warpage exceeding 1-2mm during processing.
Die Shift Tolerance: Account for die movement during molding; typical compensation logic requires accurate measurement of die position before RDL patterning.
UBM (Under Bump Metallization) Specs: Check UBM diameter and composition (Ti/Cu/Ni) to ensure robust solder ball adhesion.

When Redistribution Layer (RDL) fan-out substrate checklist applies (and when it doesn’t)

Understanding when to deploy an RDL fan-out architecture versus standard wire-bond or flip-chip packaging is the first step in the design process.

Use this checklist when:

High I/O Count is required: The design requires more I/O connections than the die footprint can support (Fan-In limit reached).
Form Factor is critical: You need the thinnest possible profile (z-height) for mobile or wearable devices.
Heterogeneous Integration: You are combining multiple dies (SiP) with different nodes into a single package using RDL interconnections.
Electrical Performance: You need shorter signal paths and lower parasitic inductance compared to wire bonding.
Thermal Management: The design benefits from direct thermal paths through the RDL to the PCB.

Do not use this checklist when:

Low Pin Count: Standard leadframe or wire-bond packages are significantly cheaper for low-complexity chips.
Extreme Power Density: Very high-power applications may require heavy copper leadframes or ceramic substrates rather than thin-film RDL.
Strict Cost Constraints: If the application does not demand high density, traditional laminate substrates (BGA) offer a lower entry cost.
Large Die Size with Low I/O: If the die is large enough to accommodate all bumps (Fan-In), Fan-Out adds unnecessary process complexity.

Redistribution Layer (RDL) fan-out substrate checklist rules and specifications (key parameters and limits)

RDL fan-out substrate checklist rules and specifications (key parameters and limits)

Following a strict set of design rules is essential for manufacturability. APTPCB (APTPCB PCB Factory) recommends adhering to these standard ranges to maximize yield.

Rule / Parameter	Recommended Value/Range	Why it matters	How to verify	If ignored
Min Line/Space (L/S)	2µm/2µm (High-end) to 10µm/10µm	Determines routing density and signal integrity.	AOI (Automated Optical Inspection)	Shorts, opens, or signal crosstalk.
Via Diameter	5µm - 20µm	Connects different RDL layers; affects resistance.	Cross-section SEM	High via resistance or open circuits.
Dielectric Thickness	5µm - 10µm per layer	Controls impedance and breakdown voltage.	Profilometer / Ellipsometry	Impedance mismatch or electrical breakdown.
Pad Pitch	40µm - 150µm	Matches the die I/O density to the RDL.	Gerber analysis	Misalignment during lithography.
Copper Thickness	3µm - 8µm	Impacts current carrying capacity and resistance.	X-Ray Fluorescence (XRF)	Overheating or trace fusing under load.
Die Shift Budget	< 10µm	Dies move during molding; litho must adapt.	Metrology inspection post-mold	Misaligned vias hitting active silicon.
Warpage Limit	< 1mm (Panel/Wafer)	Critical for handling in automated equipment.	Shadow Moiré	Handling errors, vacuum chuck failures.
UBM Diameter	200µm - 300µm (typical)	Interface for solder balls to the PCB.	Optical Microscopy	Weak solder joints, drop test failure.
Passivation Opening	> 5µm overlap	Protects Cu pads from oxidation/corrosion.	AOI	Corrosion, long-term reliability failure.
Solder Ball Material	SAC305 / SAC405	Standard lead-free alloys for reliability.	Material Cert (CoC)	Brittle joints or melting point issues.
CTE Mismatch	< 10 ppm/°C difference	Reduces stress between die, mold, and RDL.	TMA (Thermo-Mechanical Analysis)	Delamination or cracking during reflow.

Redistribution Layer (RDL) fan-out substrate checklist implementation steps (process checkpoints)

Implementing an RDL fan-out design involves a sequential build-up process. Each step requires specific validation to prevent compounding errors.

Incoming Wafer/Die Inspection (KGD)
- Action: Verify Known Good Dies (KGD) before processing.
- Key Parameter: Electrical test yield > 99%.
- Check: Map bad dies to ensure they are not placed on the carrier.
Carrier Preparation & Tape Lamination
- Action: Prepare the temporary glass or steel carrier with thermal release tape.
- Key Parameter: Adhesion strength (low enough for release, high enough for processing).
- Check: Inspect for bubbles or particles under the tape.
Die Placement (Pick and Place)
- Action: Place dies face-down on the carrier with high precision.
- Key Parameter: Placement accuracy (< ±5µm).
- Check: Optical verification of die coordinates relative to fiducials.
Compression Molding
- Action: Encapsulate dies with Epoxy Molding Compound (EMC).
- Key Parameter: Mold thickness uniformity and cure temperature.
- Check: Measure total thickness variation (TTV) and check for voiding.
Carrier Release & Debonding (if Chip-First Face-Up)
- Action: Remove carrier to expose die pads (process dependent).
- Key Parameter: Release temperature profile.
- Check: Inspect for residue on the die surface.
Dielectric Layer 1 Deposition
- Action: Spin coat or laminate photosensitive dielectric (PI/PBO).
- Key Parameter: Film thickness (e.g., 5µm).
- Check: Verify uniformity and absence of pinholes.
Lithography & Via Formation
- Action: Expose and develop vias to connect to die pads.
- Key Parameter: Exposure energy and development time.
- Check: Measure via bottom diameter and residue (scumming).
Seed Layer & RDL Plating
- Action: Sputter Ti/Cu seed layer, then electroplate copper traces.
- Key Parameter: Plating current density and bath chemistry.
- Check: Measure trace height and width (L/S verification).
Seed Layer Etching
- Action: Remove the temporary seed layer to isolate traces.
- Key Parameter: Etch rate selectivity.
- Check: Electrical test for shorts between adjacent traces.
Ball Drop & Reflow
- Action: Apply flux and place solder balls on UBM pads.
- Key Parameter: Reflow peak temperature (e.g., 245°C).
- Check: Shear test and ball coplanarity inspection.

Redistribution Layer (RDL) fan-out substrate checklist troubleshooting (failure modes and fixes)

Even with a robust checklist, defects can occur. Use this guide to diagnose and fix common RDL fan-out issues.

Symptom: Die Shift / Misalignment
- Cause: Movement of dies during the high-pressure molding process.
- Check: Compare pre-mold and post-mold coordinates.
- Fix: Optimize molding pressure/speed; use adaptive lithography scaling.
- Prevention: Use higher adhesion tape or mold underfill techniques.
Symptom: RDL Trace Cracking
- Cause: High stress due to CTE mismatch between EMC, Die, and RDL polymer.
- Check: Thermal cycling test (TCT) results; cross-section analysis.
- Fix: Select a dielectric with higher elongation; adjust EMC CTE.
- Prevention: Simulate stress using FEA (Finite Element Analysis) before design freeze.
Symptom: Delamination
- Cause: Poor adhesion between the seed layer and the dielectric or die surface.
- Check: C-SAM (Scanning Acoustic Microscopy) for interface gaps.
- Fix: Improve plasma cleaning/descum process before sputtering.
- Prevention: Monitor surface roughness and plasma chamber conditions.
Symptom: Incomplete Via Plating
- Cause: Via aspect ratio too high or air trapped in blind vias.
- Check: Cross-section SEM showing voids in vias.
- Fix: Reduce dielectric thickness or increase via diameter; optimize plating agitation.
- Prevention: Adhere to aspect ratio rules (typically < 1:1).
Symptom: Warpage Exceeding Spec
- Cause: Asymmetric stack-up or improper curing of EMC.
- Check: Shadow Moiré measurement at room and reflow temps.
- Fix: Adjust backside coating to balance stress; optimize carrier thickness.
- Prevention: Balance copper density on RDL layers.
Symptom: Electrical Opens
- Cause: Particle contamination blocking lithography or etching over-etch.
- Check: AOI defect map overlay with electrical test data.
- Fix: Improve cleanroom class; adjust etchant concentration.
- Prevention: Strict particle control and automated wafer handling.

How to choose Redistribution Layer (RDL) fan-out substrate checklist (design decisions and trade-offs)

Choosing the right RDL strategy depends on balancing performance, cost, and volume.

Chip-First vs. Chip-Last

Chip-First: Dies are placed first, then RDL is built on top. Best for yield if die shift is managed. Lower cost for standard applications.
Chip-Last (RDL-First): RDL is built on a carrier, then dies are attached. Better for high-end chips with very fine L/S because the RDL is built on a flat, stable carrier without die shift issues. Higher cost.

Wafer-Level (WLP) vs. Panel-Level (PLP)

Wafer-Level: Uses standard 300mm round wafers. Mature equipment ecosystem. Best for high-precision, smaller volume, or very high-density designs.
Panel-Level: Uses large rectangular panels (e.g., 600mm x 600mm). Higher throughput and lower cost per unit due to area efficiency. Best for mass production of consumer electronics, but equipment standards are less unified.

Dielectric Material: PI vs. PBO

Polyimide (PI): Higher cure temperature (300°C+), excellent chemical resistance. Standard for many years.
PBO: Lower cure temperature (200°C-250°C), better electrical properties (lower Dk/Df). Preferred for RF and sensitive dies.

Redistribution Layer (RDL) fan-out substrate checklist FAQ (cost, lead time, common defects, acceptance criteria, Design for Manufacturability (DFM) files)

1. What is the typical cost driver in RDL fan-out manufacturing? The primary cost drivers are the number of RDL layers (mask steps) and the yield loss from Known Good Dies (KGD) being scrapped if the final package fails. Minimizing layer count reduces cost significantly.

2. How does RDL fan-out lead time compare to standard flip-chip? RDL fan-out often has a shorter cycle time than flip-chip because it eliminates the substrate manufacturing and assembly wait times. However, NPI (New Product Introduction) lead times can be 4-8 weeks for mask generation and process tuning.

3. What are the standard acceptance criteria for RDL line width? Acceptance is usually ±10% of the nominal design width. For a 5µm line, the measured width must be between 4.5µm and 5.5µm.

4. Can I use standard Gerber files for RDL fan-out design? While Gerber files are accepted, GDSII or ODB++ formats are preferred for RDL fan-out because they handle the complex geometries and layer definitions of semiconductor-grade lithography better than standard PCB Gerbers.

5. How do I specify impedance for RDL traces? You must specify the target impedance (e.g., 50Ω) and provide the dielectric constant (Dk) of the polymer (PI/PBO). The manufacturer will adjust trace width and dielectric thickness to match.

6. What is the minimum via pitch for RDL fan-out? For standard processes, the minimum via pitch is around 10µm-15µm. Advanced processes can achieve tighter pitches, but cost increases.

7. How does APTPCB handle DFM for RDL fan-out? We review the stack-up, L/S violations, and metal density balance. See our DFM guidelines for general rules that apply to high-density interconnects.

8. Is underfill required for RDL fan-out packages? Generally, no. The molding compound acts as the protection. However, board-level underfill might be needed after mounting to the PCB for drop-test reliability.

9. What testing is performed on the finished RDL substrate? Tests include Open/Short (O/S) electrical test, AOI (Automated Optical Inspection), and visual inspection for cracks or voids.

10. Can RDL fan-out handle high-frequency RF signals? Yes. The short interconnect lengths and low-loss dielectrics (like PBO) make it excellent for 5G and mmWave applications.

11. What is the maximum number of RDL layers supported? Most designs use 1-3 layers. Going beyond 4 layers increases stress and warpage risk significantly, requiring careful CTE balancing.

12. How do I validate the reliability of my RDL design? Standard JEDEC reliability tests (Temperature Cycling, HAST, Drop Test) are required. Ensure your design passes simulation before fabrication.

HDI PCB Capabilities: Understand high-density interconnects which share similar design principles with RDL.
Advanced PCB Manufacturing: Explore other advanced packaging and substrate technologies available at APTPCB.
BGA & Fine Pitch Assembly: Learn about the assembly challenges for fine-pitch components that RDL fan-out packages often replace or interface with.

Redistribution Layer (RDL) fan-out substrate checklist glossary (key terms)

Term	Definition
RDL (Redistribution Layer)	Metal layers deposited on a die or wafer to reroute I/O pads to new locations.
Fan-Out	Packaging technology where I/O connections extend beyond the physical edge of the die.
Fan-In	Packaging where all I/O connections are located within the die perimeter.
EMC (Epoxy Molding Compound)	The encapsulant material used to protect the die and form the package body.
UBM (Under Bump Metallization)	The metal interface layer between the copper pad and the solder ball.
L/S (Line/Space)	The width of a metal trace and the distance to the adjacent trace.
KGD (Known Good Die)	Bare dies that have been tested and verified functional before packaging.
CTE (Coefficient of Thermal Expansion)	A measure of how much a material expands with temperature; critical for reliability.
Die Shift	The unintended movement of the die during the molding process.
PBO (Polybenzoxazole)	A high-performance dielectric polymer used for RDL layers.
PI (Polyimide)	A common photosensitive polymer used as a dielectric in RDL structures.
Seed Layer	A thin metal layer (usually Ti/Cu) sputtered to enable electroplating.

Request a quote for Redistribution Layer (RDL) fan-out substrate checklist (Design for Manufacturability (DFM) review + pricing)

Ready to move your design from concept to production? APTPCB provides comprehensive DFM reviews and competitive pricing for advanced packaging and high-density substrates.

To get an accurate quote, please provide:

Design Data: GDSII, ODB++, or Gerber files.
Stack-up: Desired layer count, dielectric thickness, and material preference (PI vs PBO).
Volume: Prototype quantity vs. mass production targets.
Special Requirements: Impedance control, specific surface finishes, or testing protocols.

Conclusion (next steps)

Successfully navigating the RDL fan-out substrate checklist requires a disciplined approach to design rules, material selection, and process validation. By adhering to the specifications for L/S, via formation, and warpage control outlined in this guide, engineers can achieve high-yield, reliable advanced packaging solutions. Whether you are prototyping a new SiP or scaling a mobile processor, rigorous attention to these checklist items ensures your product meets the demands of modern electronics.