PCB and PCBA Yield Analytics Workflow

PCB and PCBA Yield Analytics Workflow

A PCB/PCBA yield analytics workflow connects serialized units, process steps, inspections, tests, defects and rework into a controlled dataset that teams can use to contain escapes and improve the process. A dashboard is useful only when definitions, denominators and defect dispositions are consistent.

Key takeaways

  • Define unit, opportunity, pass, rework, retest, scrap and false call before calculating yield.
  • First-pass yield (FPY) should exclude rework/retest recovery; final yield should be reported separately.
  • Rolled throughput yield multiplies step yields and exposes cumulative loss hidden by final pass rate.
  • Separate process defect, design issue, component issue, test-system issue and handling damage.
  • Link every record to product revision, lot/panel, machine/program, material and timestamp.
  • Use Pareto analysis for prioritization, then verify root cause with evidence and a control plan.

Core metrics and definitions

Metric Definition Decision it supports
FPY Units passing a step first time / units entering the step Process performance without recovery
Final yield Accepted units / started units after allowed rework/retest Delivery output
Rolled throughput yield Product of FPY across sequential steps Total hidden factory impact
Defects per unit Confirmed defects / inspected units Defect density trend
DPMO Defects / total defined opportunities × 1,000,000 Opportunity-normalized comparison
False-call rate Inspection/test calls not confirmed as defects / total calls Inspection-program effectiveness
Escape rate Defects found downstream / units or opportunities shipped from prior gate Detection/control effectiveness

Never compare DPMO between products unless “opportunity” is defined consistently.

Minimum traceability model

Capture:

  • product, PCB and BOM revision;
  • serial/lot/panel and position;
  • material/component lot and approved substitution;
  • machine, line, recipe/program and software version;
  • operator where process requires it;
  • timestamp and environmental/process parameters;
  • inspection/test result, measured values and limit revision;
  • defect code, location, evidence, disposition and rework history.

Practical analytics workflow

  1. Validate data completeness and remove duplicate/retest ambiguity.
  2. Calculate FPY by process, product, revision, line and time window.
  3. Build a Pareto of confirmed defects, not raw machine calls.
  4. Stratify the top defect by location, package, material lot, machine, program and panel position.
  5. Contain affected WIP and shipped risk using traceability.
  6. Confirm root cause through inspection, measurement or controlled experiment.
  7. Implement corrective action and update PFMEA/control plan/work instructions.
  8. Verify effectiveness over a defined volume/time and watch for side effects.

Defect taxonomy that supports action

Level Example
Process Printing, placement, reflow, soldering, cleaning, test
Defect Insufficient paste, offset, open, bridge, void, polarity, no fault found
Location Refdes/pin/net, panel position and board region
Cause class Design, material, machine, method, measurement, environment, handling
Disposition Use-as-is, rework, repair, scrap, return or engineering review

Free-text comments can supplement but should not replace controlled codes.

Common analytics failures

Failure Consequence Better control
Retest counted as a new unit Inflated denominator and yield Serialized unit genealogy
AOI false calls treated as defects Wrong Pareto priorities Confirmed-defect field
Revision mixed in one trend Design change looks like process drift Revision filter/change marker
Only final test tracked Upstream rework cost is hidden Step-level FPY and RTY
Dashboard without containment Insight arrives after more escapes Alert and ownership workflow

Yield-data RFQ and quality checklist

  • Unit/lot/panel serialization and genealogy requirement
  • Process gates and required measured-value retention
  • Defect taxonomy and customer-specific codes
  • FPY/final-yield/rework/scrap reporting definitions
  • Traceability fields and record-retention period
  • Alert, containment and notification thresholds
  • First-article, control plan, PFMEA and change-notification scope
  • Data export/API/portal format and access control
  • Corrective-action format and effectiveness evidence

Review PCB testing and quality and submit program requirements through the PCB quotation page.

Standards and references

  • IPC-CFX / IPC-2591 — Connected Factory Exchange
  • IPC-HERMES-9852 — Machine-to-machine communication in electronics assembly
  • IPC J-STD-001 — Requirements for soldered assemblies
  • IPC-A-610 — Acceptability of electronic assemblies
  • IPC-7912 — End-item DPMO and manufacturing quality data

Confirm current revisions and customer-specific metric definitions.

Yield analytics FAQ

What is the difference between first-pass and final yield?

First-pass yield counts units passing without rework or retest. Final yield includes units recovered through the allowed process.

Should AOI calls count as defects?

Only confirmed defects should drive defect yield. Track false calls separately to improve the inspection program.

What is rolled throughput yield?

It is the product of first-pass yields across sequential process steps and shows cumulative process loss.

Can two products' DPMO be compared directly?

Only if defect opportunities and counting rules are defined consistently.

What data is essential for root cause?

Product/revision, unit/panel position, process/machine/program, material lots, timestamp, measured result, defect location and disposition are core fields.