Signal Integrity Engineering
From USB and HDMI routing on a compact IoT prototype to 112G PAM4 differential pairs on a 64-layer data center switch fabric, every high-speed design hinges on precise impedance control. APTPCB delivers impedance-controlled PCBs across all structure types, including single-ended, differential, and coplanar waveguide, with tolerances as tight as ±5Ω and 100% TDR verification on every production panel before shipment.
Core Discipline
As a manufacturer trusted by signal integrity engineers across North America, Europe, and the Asia-Pacific, APTPCB delivers production-grade controlled impedance on every board type, from standard 4-layer FR-4 to complex 64-layer hybrid stack-ups mixing Rogers RF laminates with low-loss digital cores. Whether you are a hardware startup in Silicon Valley routing USB4 on a compact wearable, or a telecom infrastructure team in Stockholm designing 400G Ethernet switch fabrics with ±5Ω differential tolerance, our CAM engineers ensure your impedance targets are met from first prototype through volume production.
Our closed-loop impedance process covers the full workflow: we simulate every impedance structure using industry-standard 2D field-solver suites with frequency-dependent Dk/Df data from the actual laminate lot, compensate trace widths for factory-specific etch factors and copper profiles, place dedicated TDR test coupons on every production panel, and deliver a measured impedance report with each shipment. We support all mainstream laminates on the market — from standard FR-4 through ultra-low-loss Megtron 6/7, Rogers PTFE, Taconic, and polyimide flex — and can source any specified material per your BOM requirements.
Impedance Structures
Every high-speed protocol specifies a particular impedance structure. We fabricate all standard and advanced configurations with full simulation support.
| Structure Type | Description | Typical Targets | Common Protocols |
|---|---|---|---|
| Single-Ended Microstrip | One signal trace on an outer layer referenced to a ground plane directly below. The simplest and most common impedance structure. | 50Ω, 75Ω | General I/O, clock signals, RF feeds, coaxial-to-PCB transitions |
| Single-Ended Stripline | One signal trace sandwiched between two reference planes on inner layers. Provides better shielding and lower EMI than microstrip. | 50Ω, 60Ω | Sensitive analog, inner-layer clocks, controlled-impedance bus lines |
| Edge-Coupled Differential Microstrip | Two parallel traces on an outer layer, tightly coupled side by side. Coupling reduces crosstalk susceptibility and provides common-mode noise rejection. | 90Ω, 100Ω | USB 2.0/3.x, HDMI, DisplayPort, LVDS, MIPI |
| Edge-Coupled Differential Stripline | Two parallel traces between reference planes. Offers the tightest impedance uniformity and best EMI performance for high-speed differential pairs. | 85Ω, 90Ω, 100Ω | PCIe Gen3/4/5/6, 10G/25G/100G Ethernet, DDR4/DDR5 |
| Broadside-Coupled Differential Stripline | Two traces stacked vertically on adjacent layers sharing reference planes. Saves routing space where horizontal coupling is not feasible. | 90Ω, 100Ω | Dense BGA breakout, high-channel-count backplanes |
| Coplanar Waveguide (CPWG) | Signal trace flanked by coplanar ground on the same layer, with an additional ground plane below. Used in RF and mmWave designs for precise impedance control at high frequencies. | 50Ω | 5G mmWave, automotive radar (77 GHz), WLAN, GPS front-ends |
| Coplanar Stripline | Coplanar waveguide buried between two reference planes. Combines coplanar shielding with stripline isolation for the best RF isolation in high-frequency PCB designs. | 50Ω | Phased-array radar, satellite transponders, test & measurement |
We also support asymmetric impedance structures, embedded resistor impedance matching, and custom target values outside standard ranges. <a href="/en/quote">Contact our SI team</a> for non-standard requirements.
Design Reference
Quick reference for impedance targets defined by common high-speed interface standards. These values must be met within the specified tolerance on the finished board.
| Interface / Protocol | Impedance Type | Target (Ω) | Typical Tolerance | Notes |
|---|---|---|---|---|
| USB 2.0 | Differential | 90 | ± 10% | 480 Mbps max; microstrip acceptable for most designs |
| USB 3.x / USB4 | Differential | 85 – 90 | ± 8% | 5 – 40 Gbps; tighter etch control needed; stripline preferred at 20 Gbps+ |
| PCIe Gen3 / Gen4 | Differential | 85 – 100 | ± 10% | 8 – 16 GT/s; requires symmetric stack-up for consistent Dk |
| PCIe Gen5 / Gen6 | Differential | 85 – 100 | ± 5% | 32 – 64 GT/s; spread-glass prepreg and ultra-low-loss laminates strongly recommended |
| DDR4 | Single-ended | 40 – 60 | ± 10% | Data lines typically 40Ω, clock/address 50Ω; JEDEC defined |
| DDR5 | Differential (clk) / SE (data) | 40 / 50 | ± 8% | Decision feedback equalization allows slightly more flexibility |
| HDMI 2.1 | Differential | 100 | ± 10% | 48 Gbps; TMDS/FRL lanes; keep stub lengths under 100 mil |
| 10GBASE-KR Ethernet | Differential | 100 | ± 8% | Backplane Ethernet; back-drilling recommended for stub removal |
| 100G / 400G Ethernet | Differential | 92 – 100 | ± 5% | PAM4 signaling; requires Megtron 6/7 or equivalent ultra-low-loss material |
| LVDS | Differential | 100 | ± 10% | Low-voltage differential signaling; common in display, camera, industrial I/O |
| MIPI D-PHY / C-PHY | Differential | 80 – 100 | ± 10% | Mobile camera / display interface; short trace lengths typical |
| SATA III | Differential | 85 – 100 | ± 10% | 6 Gbps; relatively forgiving but impedance matching still critical at connector transitions |
| 50Ω RF (Coaxial Transition) | Single-ended / CPWG | 50 | ± 5% | SMA/U.FL launch; CPWG structure preferred; see Rogers RF laminates |
Impedance Engineering
Impedance is not a single variable — it is the result of multiple interacting physical parameters that must be controlled simultaneously during fabrication.
Wider traces lower impedance; thicker copper (½ oz vs 1 oz vs 2 oz) also shifts the value. During etching, copper traces develop a trapezoidal cross-section rather than a perfect rectangle. Our CAM team compensates for this etch factor — typically 0.5 to 1.5 mil of width adjustment — using factory-calibrated correction tables for each copper weight.
The distance between trace and reference plane, combined with the dielectric constant (Dk) of the insulating material, is the most influential impedance factor. Different prepreg styles (1080, 2116, 7628) and resin systems (standard FR-4 Dk ≈ 4.2 – 4.5, Megtron 6 Dk ≈ 3.71, Rogers RO4350B Dk ≈ 3.48) produce different impedance outcomes for the same trace geometry.
For differential impedance, the gap between the two traces is critical. Tighter coupling (smaller gap) reduces differential impedance and improves common-mode rejection. We simulate the exact spacing using the chosen material's Dk at your operating frequency, then lock the gap dimension in our photoplot to prevent drift during imaging and etching.
Standard woven fiberglass creates a periodic Dk variation — traces over a glass bundle see higher Dk than traces over resin pockets. This causes intra-pair skew in differential pairs above 10 Gbps. We mitigate this by specifying spread-glass fabrics (1035, 1067, 1078 weaves) or by applying trace angle rotation in routing guidelines.
Solder mask applied over outer-layer microstrip traces adds a dielectric coating that lowers impedance by 1 – 3Ω compared to bare copper. The surface finish (ENIG, OSP, immersion tin, HASL) also affects the conductor surface roughness. We factor solder mask thickness and finish type into every outer-layer impedance simulation.
Material Dk varies with both temperature and frequency. A board simulated at 1 GHz using Dk = 4.2 may show different impedance when tested at 10 GHz where Dk may drop to 4.0. We use frequency-dependent Dk/Df data from laminate manufacturers — not just the generic "@ 1 MHz" catalog value — to ensure simulation accuracy at your actual operating frequency.
Closed-Loop Process
Our impedance control workflow is a closed loop with no gaps. Before production begins, we build a precise cross-section model in our 2D field-solver suite — inputting the actual Dk/Df data from the laminate manufacturer's datasheet at your operating frequency, the specific prepreg style and resin content, the target copper weight, and the factory's measured etch factor for that copper thickness. The solver calculates the exact trace width and spacing needed to hit your impedance target.
After fabrication, we measure every production panel using Time-Domain Reflectometry (TDR). Dedicated test coupons — mirroring your board's actual trace geometry, layer, and dielectric — are placed on the panel margins. The TDR instrument sends a fast-rise pulse down the coupon and maps the impedance at every point. If the measured value falls outside your specified tolerance, the panel is rejected. The TDR report is included with every shipment.
For IPC Class 3 aerospace and medical builds, we also perform microsection analysis to physically verify dielectric thickness and copper profile under a metallurgical microscope, providing photographic evidence that the as-built stack-up matches the simulation model.
Manufacturing Capability
Our process controls and equipment enable repeatable impedance accuracy across the full range of board types and materials.
| Parameter | Standard | Advanced | Notes |
|---|---|---|---|
| Impedance Tolerance | ± 10% (single-ended > 50Ω) | ± 5Ω (≤ 50Ω), ± 7% (> 50Ω) | Per APTPCB standard; applies to both single-ended and differential structures |
| Supported Structures | Microstrip, Stripline | All types incl. CPWG, Broadside, Asymmetric | Coplanar waveguide structures require coplanar ground fill with controlled gap |
| Minimum Trace Width | 3.5 mil (89 µm) | 2 mil (51 µm) | 2/2 mil trace/space on both inner and outer layers; impedance-controlled traces at 2 mil require LDI imaging |
| Minimum Diff. Pair Gap | 4 mil (100 µm) | 2 mil (51 µm) | Tighter gaps need controlled etch compensation; high-layer-count builds may require wider gaps for registration |
| Dk Range Supported | FR-4: 3.8 – 4.6 | PTFE/Rogers: 2.2 – 10.2 | All mainstream laminates supported per customer BOM — standard FR-4, high-Tg, low-loss, ultra-low-loss, PTFE, ceramic-filled, polyimide, and any commercially available material can be sourced to match your requirements |
| TDR Equipment Rise Time | 200 ps | 35 ps | 35 ps rise time resolves impedance discontinuities as small as 2 mm along the trace |
| Coupon Types | Panel-edge coupons | Embedded in-board coupons | In-board coupons available for military/aerospace programs requiring per-board traceability |
| Frequency-Dependent Simulation | Up to 6 GHz | Up to 70 GHz | For mmWave applications; uses manufacturer-measured Dk/Df at actual frequency band |
| Copper Roughness Modeling | Standard foil (RTF) | HVLP / VLP / Profile-free | Surface roughness adds 5 – 15% insertion loss at frequencies above 10 GHz; surface finish selection impacts this |
Upload your Gerber files or stack-up drawing — our CAM team will provide a detailed impedance simulation report and DFM review within one business day.
Material Properties
The dielectric constant (Dk) and dissipation factor (Df) of your chosen laminate directly determine trace impedance and signal loss. We maintain inventory and pressing recipes for all major material systems.
| Material Family | Representative Grades | Dk (@ 10 GHz) | Df (@ 10 GHz) | Best For |
|---|---|---|---|---|
| Standard FR-4 | Shengyi S1000-2, ITEQ IT-180A, Nan Ya NPG-170, Ventec VT-47, KB-6167F | 4.2 – 4.5 | 0.018 – 0.025 | General digital up to ~3 Gbps; cost-sensitive designs |
| Mid-Loss FR-4 | Isola 370HR, Shengyi S1000-2ME, ITEQ IT-958G, Ventec VT-481 | 3.9 – 4.2 | 0.010 – 0.015 | 10G Ethernet, PCIe Gen3/4, DDR4/DDR5 |
| Low-Loss | Megtron 4 (R-5775K), Isola I-Tera MT40, ITEQ IT-968, Nelco N7000-2 HT | 3.6 – 3.9 | 0.005 – 0.009 | 25G/50G SerDes, PCIe Gen5, high-speed backplanes |
| Ultra-Low-Loss | Megtron 6 (R-5775G), Megtron 7, Isola I-Speed, Tachyon 100G, Shengyi S7439G | 3.4 – 3.7 | 0.002 – 0.005 | 100G/400G data center, PCIe Gen6, 56G/112G PAM4 |
| PTFE / Ceramic-Filled | Rogers RO4350B, RO4835, RO3003, RT/duroid 5880, Taconic RF-35, TLY, Arlon AD255, DiClad 880 | 2.2 – 3.66 | 0.001 – 0.004 | Automotive radar, 5G mmWave, satellite, RF front-ends |
| Polyimide (Flex) | DuPont Pyralux AP/LF/HT, Panasonic Felios R-F775, Shengyi SF305C, Taiflex, Doosan | 3.2 – 3.5 | 0.005 – 0.010 | Rigid-flex impedance-controlled flex tails; dynamic bending applications |
Dk/Df values are approximate at 10 GHz per manufacturer datasheets. Actual values vary with resin content, glass style, and measurement method. The materials listed above are representative examples — APTPCB supports all mainstream rigid and flex laminates on the market and can source any commercially available material per your BOM. Our simulation uses the exact laminate lot data provided by the material supplier.
Applications
PAM4 signaling at 56G/112G per lane demands tight differential impedance on ultra-low-loss laminates with HVLP copper and back-drilled via stubs.
77 GHz radar modules require CPWG structures on Rogers or Taconic PTFE with tight impedance tolerance. EV battery management systems need impedance-matched CAN/LIN buses on heavy copper boards up to 20 oz.
MIL-PRF-31032 and IPC-6012DS Class 3/A boards with per-coupon TDR traceability, microsection verification, and the tightest impedance tolerance on polyimide or high-Tg hybrid stack-ups.
Ultrasound transducer boards and CT/MRI data acquisition systems with differential impedance control on noise-sensitive analog channels. IPC Class 3 reliability with full impedance documentation.
Hybrid stack-ups mixing RF front-end layers on Rogers with digital baseband on low-loss FR-4. CPWG and microstrip impedance must be consistent from DC to 40+ GHz across operating temperature range.
Compact HDI boards with fine-pitch BGA breakout requiring impedance-controlled microvias and stripline pairs on ultra-thin dielectrics down to 2 mil.
Design Best Practices
Successful impedance control starts at the schematic and layout stage — long before the board reaches the factory. Engineers should define impedance targets for each signal class in their constraint manager and communicate these requirements clearly on the fabrication drawing. A well-documented impedance table listing the layer, structure type, target value, tolerance, and trace width/spacing intent prevents ambiguity and reduces DFM iterations.
Maintain consistent trace width along the entire impedance-controlled net. Avoid necking down differential pairs at via transitions unless absolutely necessary, and when you must, keep the necked region as short as possible (ideally under 50 mil). Route differential pairs with matched length within ±5 mil per pair, and maintain at least 3× the trace width as clearance from adjacent signals to minimize crosstalk coupling.
Every impedance-controlled trace needs a continuous, unbroken reference plane directly adjacent. Splits, slots, or excessive via anti-pads in the reference plane create impedance discontinuities that no amount of trace-width tuning can fix. When a signal must cross a plane split, bridge it with stitching capacitors and accept that impedance will be degraded in that region. For multilayer stack-ups, dedicate full planes to ground rather than splitting power and ground on the same layer.
Through-hole vias introduce a capacitive discontinuity in impedance-controlled paths. For signals above 10 Gbps, use back-drilled vias or blind/buried microvias to eliminate the via stub. Place ground vias adjacent to signal vias (within 10 mil) to maintain the return-current path. In differential pairs, keep via-to-via spacing identical to the trace-to-trace spacing to preserve the differential impedance through the transition.
Include a clear impedance control table on your fab drawing specifying: layer number, structure type (microstrip/stripline/CPWG), single-ended or differential, target impedance in Ohms, tolerance (±5/8/10%), and reference layer. Also note any layers where solder mask should be opened over impedance traces. This documentation enables our CAM team to run accurate simulations and propose trace-width adjustments before production — reducing your time to first-article approval.
FAQ
Interactive Tool
Select an impedance structure type to see the typical cross-section geometry, key parameters, and design considerations.
Global Engineering Reach
Signal integrity engineers across telecom, automotive, aerospace, and data center industries worldwide rely on APTPCB for precision impedance control with full TDR verification and same-day DFM review.
Data center OEMs in Silicon Valley, defense primes in the Washington D.C. corridor, and automotive Tier-1 suppliers in Michigan rely on our TDR-verified impedance-controlled boards for 100G+ switch fabrics and ADAS radar modules.
Automotive radar suppliers in Stuttgart, telecom infrastructure teams in Stockholm, and medical imaging innovators in the UK source our impedance-controlled boards with hybrid Rogers/FR-4 stack-ups.
Semiconductor companies and server OEMs across APAC utilize our impedance simulation and TDR verification services for high-speed SerDes validation before volume production release.
Defense electronics and satellite communication programs in the region rely on our CPWG impedance control on PTFE laminates with full microsection documentation and MIL-spec traceability.
Share your Gerber data, impedance targets, and material preference. Our CAM team will return a detailed impedance simulation report, trace-width adjustment recommendations, and quotation within one business day.
